PARALLEL ARCHITECTURES: A BRIEF INTRODUCTION in Java

Printer Data Matrix in Java PARALLEL ARCHITECTURES: A BRIEF INTRODUCTION
22 PARALLEL ARCHITECTURES: A BRIEF INTRODUCTION
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There are dozens of different parallel architectures, among them networks of workstations, clusters of off the shelf PCs, massively parallel supercomputers, tightly coupled symmetric multiprocessors, and multiprocessor workstations In this section, we give an overview of these systems, focusing on the characteristics relevant to the programmer 221 Flynn's Taxonomy By far the most common way to characterize these architectures is Flynn's taxonomy [Fly72] He categorizes all computers according to the number of instruction streams and data streams they have, where a stream is a sequence of instructions or data on which a computer operates In Flynn's taxonomy, there are four possibilities: SISD, SIMD, MISD, and MIMD
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Single Instruction, Single Data (SISD) In a SISD system, one stream of instructions processes a single stream of data, as shown in Fig 21 This is the common von Neumann model used in virtually all single processor computers
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Figure 21 The Single Instruction, Single Data (SISD) architecture
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Single Instruction, Multiple Data (SIMD) In a SIMD system, a single instruction stream is concurrently broadcast to multiple processors, each with its own data stream (as shown in Fig 22) The original systems from Thinking Machines and MasPar can be classified as SIMD The CPP DAP Gamma II and Quadrics Apemille are more recent examples; these are typically deployed in specialized applications, such as digital signal processing, that are suited to fine grained parallelism and require little interprocess communication Vector processors, which operate on vector data in a pipelined fashion, can also be categorized as SIMD Exploiting this parallelism is usually done by the compiler
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Figure 22 The Single Instruction, Multiple Data (SIMD) architecture
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Multiple Instruction, Single Data (MISD) No well known systems fit this designation It is mentioned for the sake of completeness Multiple Instruction, Multiple Data (MIMD) In a MIMD system, each processing element has its own stream of instructions operating on its own data This architecture, shown in Fig 23, is the most general of the architectures in that each of the other cases can be mapped onto the MIMD architecture The vast majority of modern parallel systems fit into this category
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Figure 23 The Multiple Instruction, Multiple Data (MIMD) architecture
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222 A Further Breakdown of M IMD The MIMD category of Flynn's taxonomy is too broad to be useful on its own; this category is typically decomposed according to memory organization Shared memory In a shared memory system, all processes share a single address space and communicate with each other by writing and reading shared variables One class of shared memory systems is called SMPs (symmetric multiprocessors) As shown in Fig 24, all processors share a connection to a common memory and access all memory locations at equal speeds SMP systems are arguably the easiest parallel systems to program because programmers do not need to distribute data structures among processors Because increasing the number of processors increases contention for the memory, the processor/memory bandwidth is typically a limiting factor Thus, SMP systems do not scale well and are limited to small numbers of processors
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Figure 24 The Symmetric Multiprocessor (SMP) architecture
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The other main class of shared memory systems is called NUMA (nonuniform memory access) As shown in Fig 25, the memory is shared; that is, it is uniformly addressable from all processors, but some blocks of memory may be physically more closely associated with some processors than others This reduces the memory bandwidth bottleneck and allows systems with more processors; however, as a result, the access time from a processor to a memory location can be significantly different depending on how "close" the memory location is to the processor To mitigate the effects of nonuniform access, each processor has a cache, along with a protocol to keep cache entries coherent Hence, another name for these architectures is cache coherent nonuniform memory access systems (ccNUMA) Logically, programming a ccNUMA system is the same as programming an SMP, but to obtain the best performance, the programmer will need to be more careful about locality issues and cache effects
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