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[CHER86] J. S. Chern, P. Yang, P. Patnaik, and J. A. Seitchik, Alpha-Particle-Induced Charge Transfer between Closely Spaced Memory Cells, IEEE Trans. Electr. Devices, ED-33 (June 1986): 822 834. [CLIF74] R. A. Cliff and T. R. N. Rao, Improving the Yield of LSI Memory Chips by the Application of Coding, Proc. 8th Ann. Princeton Conf. Info. Sci. Syst. (1974): 386 390. [CLIF80] R. A. Cliff, Acceptable Testing of VLSI Components Which Contain Error Correctors, IEEE J. Solid-State Circ., SC-15 (February 1980): 61 70. [DAVI85] L. Davis, A Word-Wide 1Mb ROM with Error Correction, Dig., 1985 IEEE Int. SolidState Circ. Conf., WAM3.2 (February 1985): 40 41. [DAVY91] A. A. Davydov and L. M. Tombak, An Alternative to the Hamming Code in the Class of SEC-DED Codes in Semiconductor Memory, IEEE Trans. Info. Theory, 37 (May 1991): 897 902. [DEZA82] K. Dezaki and H. Imai, Error Control for Main Memories Using Parity Checkers in Memory Chips (in Japanese), Trans. IECE Japan, J65-D (August 1982): 1034 1040. [EGAW80] Y. Egawa, T. Wanda, Y. Ohmori, N. Tsuda, and K. Masuda, A 1-Mbit Full-Wafer MOS RAM, IEEE J. Solid-State Circ., SC-15 (August 1980): 677 686. [FIFI91] J. A. Fi eld and C. H. Stapper, High-Speed On-Chip ECC for Synergistic Fault-Tolerant Memory Chips, IEEE J. Solid-State Circ., 26 (October 1991): 1449 1452. [FUJA85] T. Fuja. C. Heegard, and R. Goodman, Some Linear Sum Codes for Random Access Memories, Proc. IEEE Int. Symp. Info. Theory (June 1985). [FUJI75] E. Fujiwara and K. Aoki, Reliability of Main Memories (in Japanese), J. Info. Proc. Soc. Japan, 16 (April 1975): 295 304. [FUJI76] E. Fujiwara and T. Kawakami, A Memory Having Double Error Correction Capability Sequential Correction for BCH Code, (in Japanese). Paper of Technical Group, IECE Japan, EC 76 20 (June 1976). [FUJI78] E. Fujiwara, Odd-Weigh-Column b-Adjacent Error Correcting Codes, Trans. IECE Japan, E61 (October 1978): 781 787. [FUJI80] E. Fujiwara and K. Haruta, Design of Main Storage Error Checking and Correcting Circuit for LSI Implementation (in Japanese), Trans. IECE Japan, 63-D (February 1980): 129 136. [FUJI81] E. Fujiwara, Error Correcting Code and its Application to Digital Systems (in Japanese), PhD dissertation, Tokyo Institute of Technology (April 1981). [FUJI82] E. Fujiwara and S. Kaneda, Application of Error Correcting Codes for Increasing Computer System Reliability (in Japanese), J. Info. Process. Soc. (IPS) Japan, 23 (April 1982): 292 298. [FUJI90] E. Fujiwara, in H. Imai (ed.), Essentials of Error-Correcting Coding Techniques, Academic Press (1990), ch. 4. [FURU89] K. Furutani, K. Arimoto, H. Miyamoto, T. Kobayashi, K. Yasuda, and K. Mashiko, A Built-in Hamming Code ECC Circuit for DRAM s, IEEE J. Solid-State Circ., 24 (February 1989): 50 56. [GHAF84] K. A. Ghaffar and R. J. McEliece, Soft Error Correction for Increased Densities in VLSI Memories, Proc. 11th IEEE Int. Symp. on Computer Architecture (1984): 248 250. [GOLA83] P. Golan and J. Hlavika, A Method for Parallel Decoding of Double-Error Correcting Group Codes, Dig., 13th IEEE Int. Symp. on Fault-Tolerant Computing (June 1983): 338 341. [HAMM50] R. W. Hamming, Error Detecting and Error Correcting Codes, Bell Syst. Techn. J., 26 (April 1950): 147 160. [HAN87] S. H. Han and M. Molek, A New Technique for Error Detection and Correction in Semiconductor Memories, Proc. IEEE Int. Test Conf. (1987): 864 870.
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[HORI75] T. Horiguchi and K. Morita, A Parallel Memory with Double Error Correction Capability A Class of One-Step Majority-Logic Decodable Error Correction Codes (in Japanese), Paper of Technical Group IECE Japan, EC 75 42 (November 1975). [HORI76] T. Horiguchi, A Double Error Correcting Code in Main Memory On Parallel Decoding of DEC-Melas Codes and BCH Codes (in Japanese), Paper of Technical Group IECE Japan, EC76-61 (November 1976). [HOWE77] T. H. Howell, G. E. Cregg, and L. Rabins, Table Lookup Direct Decoder for DoubleError Correcting DEC BCH Codes Using a Pair of Syndromes, US Patent 4030067 (June 14, 1977). [HSIA69] M. Y. Hsiao and J. T. Tou, Application of Error-Correcting Codes in Computer Reliability Studies, IEEE Trans. Reliability, R-18 (August 1969): 108 118. [HSIA70a] M. Y. Hsiao, A Class of Optimal Minimum Odd-Weight-Column SEC-DED Codes, IBM J. Res. Dev., 14 (July 1970): 395 401. [HSIA70b] M. Y. Hsiao, D. C. Bossen, and R. T. Chen, Orthogonal Latin Square Codes, IBM J. Res. Dev., 14 (July 1970): 390 394. [IMAI77a] H. Imai and Y. Kamiyanagi, On Parallel Decoders for Double-Error-Correcting BCH Codes (in Japanese), Trans. IECE Japan, J60-D (September 1977): 761 762. [IMAI77b] H. Imai and Y. Kamiyanagi, A Construction Method for Double-Error Correcting Codes for Application to Main Memories (in Japanese), Trans. IECE Japan, J60-D (October 1977): 861 868. [IMAI79] H. Imai and H. Fujiya, A Construction Method for Simple-Decodable Error-Correcting Codes (in Japanese), Trans. IECE Japan, J62-A (May 1979): 271 277. [KALT90] H. L. Kalter, C. H. Stapper, J. E. Barth, J. D. Lorenzo, C. E. Drake, J. A. Fi eld, G. A. Kelley Jr., S. C. Lewis, W. B. Van den Hoeven, and J. A. Yankosky, A 50-ns 16-Mb DRAM with a 10-ns Data Rate and On-Chip ECC, IEEE J. Solid-State Circ., 25 (October 1990): 1118 1128. [KANE84] S. Kaneda and H. Fukuda, Reliability Design of Memory Systems Considering SoftError (in Japanese), Trans. IECE Japan, J67-D (September 1984): 1036 1043. [KITA80] Y. Kitano, S. Kohda, H. Kikuchi, and S. Sakai, A 4-Mbit Full-Wafer ROM, IEEE J. Solid-State Circ., SC-15 (August 1980): 686 693. [LEIG82] F. T. Leighton and C. E. Leiserson, Wafer Scale Integration of Systolic Arrays, Proc. 23rd IEEE Symp. on Foundation of Computer Science (1982): 297 311. [MANG84a] T. E. Mangir, Sources of Failures and Yield Improvement for VLSI and Restructurable Interconnects for RVLSI and WSI: Part I Sources of Failures and Yield Improvement for VLSI, Proc. IEEE, 72 (June 1984): 690 708. [MANG84b] T. E. Mangir, Sources of Failures and Yield Improvement for VLSI and Restructurable Interconnects for RVLSI and WSI: Part II Restructurable Interconnects for RVLSI and WSI, Proc. IEEE, 72 (December 1984): 1687 1694. [MANO82] T. Mano, M. Wada, N. Ieda, and M. Tanimoto, A Redundancy Circuit for a FaultTolerant 256K MOS RAM, IEEE J. Solid-State Circ., SC-17 (August 1982): 726 731. [MANO83] T. Mano, J. Yamada, J. Inoue, and S. Nakajima, Circuit Techniques for a VLSI Memory, IEEE J. Solid-State Circ., SC-18 (October 1983): 463 470. [MANO87] T. Mano, T. Matsumura, J. Yamada, J. Inoue, S. Nakajima, K. Minegishi, K. Miura, T. Matsuda, C. Hashimoto, and H. Namatsu, Circuit Technologies for 16Mb DRAMs, Dig., 1987 IEEE Int. Solid-State Circuit Conf. (February 1987): 22 23. [MATS77] K. Matsuzawa and Y. Tohma, A Way of Multiple Error Correction for Computer Main Memory (in Japanese), Trans. IECE Japan, J60-D (October 1977): 869 876. [MATS78] K. Matsuzawa and Y. Tohma, An Adjacent-Error-Correcting Code Based on the Threshold Decoding, Dig., 8th IEEE Int. Symp. Fault-Tolerant Computing (1978): 225.
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