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Figure 4.5 Block diagram of the on-chip ECC RAM. Source: [MANO83]. 1983 IEEE.
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correction capability depends on the probability of the data stored in two or more memory cells being damaged by the a-particle within an error correction period t0 . Assume that the incidence of the a-particle s strike obeys a Poisson distribution and that the impact of single strike always generates a single-bit error. Then the soft error rate of a RAM chip with ECC is calculated as follows [MANO83]: RECC MN 2 S0 N=t0 fln 1 MNS0 t0 g; where M is the a- ux density, N 2 is the number of memory cells in a chip, and S0 is the effective memory cell area. However, the error rate of a RAM chip without ECC is R0 MN 2 S0 : The soft error rate of the 1 mega-bit (1 Mb) RAM chip with ECC is shown in Figure 4.6 and compared with the error rate without ECC. As the gure shows, the smaller the a- ux density, the greater is the improvement. The improvement factor is more than 106 at an a ux density of 1 cm 2 h 1 . Clearly, high a-particle immunity is achieved by the on-chip single-bit error correcting code. To implement an on-chip ECC circuit, it is necessary to reduce the area of the logic circuit and the decoding delay. As was mentioned before, the circuit for the on-chip ECC requires extra memory cells and decoding circuit. Among the codes with a single-bit error correction capability, we consider here a two-dimensional distance-4 cross-parity code and a distance-3 Hamming code. In a twodimensional cross-parity code, the horizontal and vertical parity bits are appended to the
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Alpha-flux density (cm
2 . 1 h )
*FIT = Number of faults occurring over 109 hours per DRAM chip t0 : Error correction period(s)
Figure 4.6 Soft error rate characteristic of the DRAM chip with an on-chip single-bit error correcting code. (Effective storage area in a single transistor cell is assumed to be 10 mm2.) Source: [MANO83]. IEEE.
CODES FOR HIGH-SPEED MEMORIES I: BIT ERROR CONTROL CODES
Horizontal parity bits Memory cells
0 1 0 1
1 0 1 1
Information bits (4 x 4)
1 0 0 1
0 1 1 0 0 1 0 0
Horizontal parity bits (4)
0 0 0 1
Vertical parity bits
Vertical parity bits (4)
Word line
Figure 4.7 Organization of a cross-parity codeword and its corresponding data in memory cells connected to a specified word line. Source: [MANO83]. 1983 IEEE.
information bits organized in a two-dimensional array. This is shown in Figure 4.7. In this case, if a single-bit error occurs in the information bits, the error can be simply corrected by horizontal and vertical parity checks. In Figure 4.7 the two-dimensional information bits and the horizontal and vertical parity bits correspond to the stored data in a set of memory cells connected to a speci ed word line. The readout word from the memory is entered to the decoding circuit, and then vertical and horizontal parity checks are performed. Each information bit is checked by twice independently, by both a vertical and a horizontal check, therefore called a cross-parity check. For example, the third information bit in the second row belongs to the second parity check in the horizontal group (H group) and also to the third parity check in the vertical group (V group). This
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Horizontal parity-bit cells Vertical parity-bit cells Group 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Informationbit cells Word line
Horizontal group selector Vertical group selector
5 1 5 1 5 1 5 1 1 1 1 5 5 5 H=