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location capability both soft errors and hard errors can be corrected [BOSS80, DEZA82], and the system will concentrate on erasure correction. Error location enables the distance-4 code (SEC-DED code) to correct up to three errors, in accordance with the discussion in Subsection 2.2.4. The following algorithm shows way to correct the case of one hard error and one soft error occurring simultaneously, in effect, hard-plus-soft errors [BOSS80]. In the algorithm the hard error is statically located during the recovery process, and an algorithmic modi cation of the original syndrome allows the correction of the soft error. In this way, no extra auxiliary storage will be required. Let h be the hard-error bit position and a be the soft-error bit position. Then the resultant syndrome Su is the exclusive-OR of the syndromes due to erroneous bits a and h, meaning Su Sa Sh . The decoding algorithm is as follows: Step 1. Detect the uncorrectable error, represented by Su, a double-error syndrome. Save the codeword with errors as well as the syndrome. Step 2. Using the exerciser diagnostic patterns, locate position h of the solid (hard) error. Knowing the index h, generate Sh . Step 3. Determine Sa Su Sh . Step 4. Decode Sa to correct bit a in the data. Invert bit h (determined in step 2) to correct the hard error. This algorithm can be implemented as shown in Figure 4.3, where (72, 64) SEC-DED code is applied. In step 2 of the algorithm three diagnostic test patterns are generally required in order to locate the hard error position in this memory system. However, if an even-weight-row SEC-DED code is applied to the system, only two test patterns are satisfactory because a bit-wise complemented codeword of the even-weight-row code is also a codeword (see Section 3.3). Hence only all-0 data and all-1 data, both of which are codewords of this code, can test the memory system. In general, how we get the error pointers is important in this technique. In the foregoing method, the pointers are obtained by applying the test patterns to the memories. It is apparent that these error pointers are available only for hard errors.
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System reliability usually decreases as the capacity of a memory system increases. To maintain the same high level of reliability, or to improve reliability, more powerful error control codes such as double-bit error correcting (DEC) code, double-bit error correcting and triple-bit error detecting (DEC-TED) code (both based on the well-known BCH code), or multiple-bit error correcting majority-logic decodable code [PETE72] may be applied to large-scale high-reliability memory systems. However, these codes generally make the decoding slower and increase code redundancy. Because of these problems some new extended codes that are based on the BCH code [PATE72a, IMAI77b, IMAI79] and the new majority-logic decodable codes [HSIA70b, CHEN73, HORI75, MATS77, MATS78] have been studied. Some modi cations to the double-bit error correcting BCH codes have been proposed in [PATE72b, FUJI76, IMAI77a, HOWE77, YAMA80, GOLA83, OKAN87].
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RDR: Read data register EPR: Error pointer register UE: Uncorrectable error
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Figure 4.3 Schematic implementation for correction of an a-particle-induced uncorrectable error. (Note: indicates exclusive-OR, or XOR.) Source: [BOSS80]. Copyright 1980 by International Business Machines Corporation;
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Table 4.3 shows the check-bit lengths of the existing codes with double-bit error correction capability. These two types of codes have the following general features: 1. BCH-based codes have a minimum or smaller number of check bits, but have complex decoding hardware and a longer decoding time. 2. Majority-logic decodable codes have a high decoding speed and simple decoding hardware, but have a large number of check bits (i.e., nearly one-half of the information-bit length).
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TABLE 4.3 Check-Bit Lengths of DEC Codes Information-bit length k (bits) Codes BCH code Imai-Kamiyanagi code [IMAI77b] Horiguchi-Morita codea [HORI75] MA codea [MATS77] Orthogonal Latin square codea [HSIA70b]
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