Codes for High-Speed Memories I: Bit Error Control Codes in .NET

Maker qrcode in .NET Codes for High-Speed Memories I: Bit Error Control Codes
Codes for High-Speed Memories I: Bit Error Control Codes
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Error control codes (ECCs) have been successfully applied to computer systems, especially to memory systems. One can say that every memory designer has adopted some types of error detecting or error correcting codes in order to enhance system reliability [HSIA69, TANG69, FUJI82, CHEN84, BOSE86B, FUJI90]. In s 4 through 7 we discuss error control codes for high-speed memories, namely for semiconductor memories such as cache memories, main memories, control memories, and disk cache memories. These memories all employ random access memory (RAM) semiconductor chips. Therefore we also call these applications codes for semiconductor memories. 4 covers bit error correcting code applications, and s 5, 6, and 7 cover some types of byte error correction / detection for recent memory systems with byte organized high-density RAM chips. One of the notable features of the codes developed for high-speed memories is that parallel encoding and decoding is required to maintain high rates of data throughput. Therefore encoding and decoding circuits have to be implemented by combinational logic [HSIA69, FUJI75]. In high-speed memories, single-bit error correcting and double-bit error detecting codes (SEC-DED codes) were commonly used. This is because the original rstgeneration semiconductor DRAM (dynamic RAM) chips are organized for one bit of data input / output at a time, and therefore any failure in one chip manifested itself as one bit in error. For the purpose of correcting soft errors induced by a-particles, external noises, and sometimes by neutrons and cosmic rays, some new techniques and some advanced error correcting codes are being required for large-capacity, high-speed memories [HSIA70b, IMAI77b, BOSS80]. This chapter deals with these considerations for codes such as the modi ed Hamming SEC-DED codes and double-bit error correcting codes (DEC codes). This chapter also presents on-chip error control codes, called on-chip ECCs, that are used to solve the problems of soft-errors and chip yield degradation.
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Code Design for Dependable Systems: Theory and Practical Applications, by Eiji Fujiwara Copyright # 2006 John Wiley & Sons, Inc.
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CODES FOR HIGH-SPEED MEMORIES I: BIT ERROR CONTROL CODES
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MODIFIED HAMMING SEC-DED CODES
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A distance-4 Hamming code [HAMM50] can correct single-bit errors and also detect double-bit errors (SEC-DED). This code can be formed by extending a distance-3 Hamming code with an overall parity check, that is, a check on all the symbols shown in Subsection 2.3.3. This section shows that this Hamming SEC-DED code can be modi ed and optimized from the practical point of view. The resulting code is called a modi ed Hamming SECDED code. This code can also be used to solve multiple soft error problems. 4.1.1 Odd-Weight-Column Codes Hsiao Codes
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The minimum distance of an SEC-DED code is 4. Since a nonzero n-tuple of weight 3 or less is not a codeword, any set of three columns of the H matrix should be linearly independent. Note that the sum of two odd-weight r-tuples is an even-weight r-tuple (i.e., odd odd even, even odd odd, even even even). Because of this property, an SEC-DED code with r check bits can be constructed with its H matrix consisting of distinct nonzero r-tuples of column vectors having odd weight [HSIA70a]. This code is different from the original Hamming SEC-DED code whose H matrix has an all-1 row vector in addition to the SEC code H matrix. Therefore this code is called a modi ed Hamming code or, more speci cally, an odd-weight-column SEC-DED code, because every H matrix column vector is odd weight. The following code design was rst proposed by M. Y. Hsiao in 1970, and therefore the code is also called Hsiao code. This code has a possibility to have minimum number of 1 s in the H matrix, which makes the hardware and the speed of the encoding / decoding circuit optimal. That is, it satis es the condition of the minimum-weight & equal-weight-row code shown in Section 3.1, and hence this code is called optimal from the practical point of view. With these considerations, the H matrix of this code is constructed as follows: r Step 1. Use all 1 weight-1 columns for the r check-bit positions. r Step 2. Next, if 3 ! k, where k is information-bit length, select k weight-3 columns out r r r of all possible 3 combinations. If 3 < k, all 3 columns should be selected. r r Step 3. For the case of 3 < k, select the leftover columns rst from among all 5 weight-5 columns. The process is continued until all k columns (corresponding to information positions) have been speci ed. If the code length n k r is exactly equal to
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