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3 3 8-bit vectors, S1 and S3 , with S1 X1 X2 , and S3 X1 X2 . Given the syndrome S1 ; S3 , the following relation holds:
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D S3 S3 1
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3 2 2 3 3 3 X1 X 1 X2 X1 X2 X2 X1 X2 2 2 X1 X2 X1 X2 X1 X2 X1 X2 2 S2 X 1 S 1 X1 : 1 2 The expression S2 X1 S1 X1 can be represented by S1 Tx, where Tx is an 8 8 binary 1 matrix uniquely determined by the position X. The double-error decoding algorithm is shown as follows:
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Step 1. Compute D S3 S3 . 1 Step 2. For each of the 144 codeword position X, compute Qx S1 Tx . The computation of all 144 Qx values can be carried out in parallel in hardware involving XOR circuits. Step 3. If Qx D for particular X, then X is a position of error. The data at position X are then corrected by an inversion of the data bit. (b) Recent Server Machines A typical server machine of IBM eServer z900 and z990, whose dependable system structure is based on the former server IBM S/390 G5 and G6, has the strategy to enable continuous reliable operation, supported by the following building blocks [MUEL99, ALVE02, FAIR04]:        Error prevention Error detection Error recovery Problem determination Service / support Change management Measurement
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These blocks provide the capabilities of self-protecting, self-healing, self-con guring, and self-optimizing. This design strategy is illustrated in Figure 12.50. Major enhancements in RAS design, concurrent upgrade and concurrent repair for the system have been made in the processor, memory, I/O, power / cooling, service / support subsystem, and so forth. The dependable techniques of duplication, N 1 redundancy and coding are extensively applied to the subsystems of processor, storage, I/O, and so forth. In the processor subsystem the processor units (PUs) each having the level-1 cache (L1 cache) and the secondary cache (L2 cache) are duplicated and are tightly coupled. Parityprediction and carry checking are applied to the adders and the arithmetic logic units (ALUs). Also residue checking is applied to the modular exponentiation engines in the cryptographic coprocessor element.
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Figure 12.50 zSeries RAS strategy building blocks and eServer self-management. Source: [ALVE02]. 2002
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by International Business Machines Corporation; republished by permission.
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In memories some type of bit or byte error correcting / detecting codes are applied to the following various storages:  Level-1 cache (L1 cache): simple parity-check code  Level-2 cache (L2 cache): (25, 19) ECC for address eld in the directory, (11, 5) ECC for ownership eld in the directory, and (72, 64) SEC-DED code for memory data eld  Main memory: minimum-weight & equal-weight-row (140, 128) S2EC-D2ED code [CHEN96] for data eld* and background scrubbing For address information, two memory address parity bits are added to prevent data from being fetched from an erroneous location. However, these address parity bits are not stored in the main memory. In another memories and the bus-line circuit, the following codes are applied:  Address translation buffer: (16, 10) SEC-DED code for each of duplicated stored data, and background scrubbing
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* The (76, 64) S4EC-DED code is applied to the former Server G3 and G4 to ensure that all single 4-bit errors in a DRAM chip with 4-bit I/O data are corrected and also random double-bit errors are detected [DOET97, SPAI99]. This type of code is presented in Section 6.2.
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CODING FOR LOGIC AND SYSTEM DESIGN
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 Bus interface between L2 cache and memory controller: simple parity-check code for command and status bus  Cryptographic key storage: triplicated key data, each appended by simple paritycheck bit Background Memory-Scrubbing and Sparing In main memories the dynamic form of sparing is performed via background scrubbing, a process of error avoidance. The memory-scrubbing process serves two functions. The rst function is to eliminate the accumulation of soft errors in the memory chip. The purpose is to reduce the likelihood of the alignments of existing soft errors and future hard or soft errors. The second function of scrubbing is to identify and record hard errors in the memory chip. Multiple hard errors are prime targets to line up in the same ECC word because they can result in uncorrectable error events. Error counts are accumulated while scrubbing, and DRAMs with high counts are spared. Once a memory chip with multiple hard errors is identi ed, a spare chip replacement is invoked to transfer data from the failing chip to the spare chip. The failing chip then is set to become inactive. The scrubbing process runs in the background, with minimal interference with the normal system operations. With up to 32 spare DRAMs per memory card, a memory card will rarely need to be replaced because of DRAM failure.
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12.4.2 Coding for VLSI Processors / Microprocessors In today s microprocessors a variety of coding techniques are being applied not only to the ALU logics and the cache memories but also to the data transfer circuits such as bus-line circuits, the register arrays, the key storage, and the address translation arrays. 1. Duplicate VLSI Processors Sedmak [SEDM80b] studied the fault tolerance of a general purpose computer utilizing very large scale integration chips. A major method of achieving fault tolerance is by internal redundancy using duplicate complementary logic. This kind of complementary duplication is used in the VLSI chips shown in Figure 12.51. In these gures it is easy to see that for a given combination logic element in the functional portion, the signals into and out of the gate are polarities, opposite to those of the complementary portion. This technique serves two purposes. First, it eliminates a problem associated with applying the same mask or cell type twice internally. The problem is that failures (designs, process, and wearout) undetected by the comparators could occur in noncomplementary duplication where a mask or cell fault might materialize in both the functional and duplicate circuits and thus create an identical failure state. Second, the design with complementary duplication will be much less susceptible to bridging faults than noncomplementary duplication. This is because there will be far fewer occurrences of long nets of metalization with the same Boolean function and the same polarity signal, which, if bridged, might result in an undetected error should a subsequent failure occur. Each of the code checkers and comparators is implemented using a self-checking design approach. The self-checking comparators shown in Figures 12.24 and 12.25 are extensively used. As a result of the cost-effectiveness of the design, the logic overhead that consists of duplicate complementary gates, comparators, and other fault detection circuits, comprises approximately 55% of the total gates in the CPU. Compared to the conventionally checked VLSI machine, the increase in chip count is only 5.5%. In this
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