Generating Quick Response Code in .NET SELF-TESTING CHECKERS
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Let the prediction functions in this example be AND, OR, and the parity function of the inputs for y0, y1 and y2 , respectively. In this case, K can be expressed as follows: 3 0000000000000001 K 40 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 0110100110010110 That is, the prediction function x0 x1 x2 x3 is adopted for y0, x0 x1 x2 x3 for y1, and x0 x1 x2 x3 for y2. Next we apply the code whose encoding matrix H is expressed as H ! 010 : 101 2
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This matrix can detect double errors, such as y0 and y1 errors, and y1 and y2 errors, as well as detect single and triple errors in Y. Given the above K and H, the checking logic can be formulated systematically as follows: Circuit I: H K ! 0111111111111111 ; 0110100110010111 x0 x1 x2 x3 x0 x1 x2 x3 x0 x1 x2 x3
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I H K U Circuit J: H A K
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J H Y H A K U ! y1 xo x1 y0 y2 x0 x1 x2 x3 x1 x2 x3 x0 x1 x3 x0 x2 x3 x1 x2 x3 ! J0 : J1 Circuit Z: Z z0 ; z1 I0 ; J0 ~ I1 ; J1 : Operation ~ is defined in Lemma 12:3: Figure 12.31 shows the GPC having the capability of detecting some double errors as well as single and triple errors. Aspx qrcode creationwith .net
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Figure 12.31 Example of a generalized prediction checker (GPC). Source: [FUJI87a]. 1987 IEEE.
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If K A, then the circuits I and J can be expressed as Circuit I : I H K U H A U; Circuit J : J H Y: We can apply the simple parity-check code to the GPC whose encoding matrix is H 1 1 1 : Then the circuits I and J can be expressed as follows. Circuit I : H A U 0101010111010101 U x0 x1 x2 x3 ; Circuit J : y0 y1 y2 : Figure 12.32 shows this checker, which is equal to the parity prediction checker shown in Figure 12.17. We now consider the method of reducing the gate amount of this checker under given matrix H. The circuit Z and the circuit J00 are determined by H. We let K A. Then the
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Figure 12.32 Example of a GPC equal to a parity prediction checker.
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circuit J0 does not exist because H A K U 0, so the circuit J000 is left out. For the circuits J0 , J00 , and J000 shown in Figure 12.30, this would reduce the gate amount of the circuit J to the minimum. In this case the checker is equivalent to the parity-based prediction checker determined by H. In general, for K 6 A, reducing the gate amount of the checker, especially in the circuits I and J0 , is basically equivalent to a logic minimization problem. For the example circuit shown in Figure 12.31, the gate amount is reduced from 44 to 18 when K is equal to A for the same matrix H. Self-testing GPC The self-testing GPC can detect faults in the checker itself. The checker will operate correctly even if single faults occur in both the circuit L and the checker CK. To make the checker self-checking, an input v that can take any value in f0; 1g is added to the checker as follows: Circuit I : Ii H K U i v; Circuit J : Ji H Y i H A K U i v; " # r 1 \ ~ Circuit Z : Z z0 ; z1 Ii ; Ji ~ v; v ;
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12:8 12:9 12:10
v 2 f0; 1g; i 0; 1; . . . ; r 1:
Theorem 12.10
The circuit determined by Eqs. (12.8) through (12.10) is code disjoint.
Input v is added to both circuits I and J, and therefore this does not affect any checking logic de ned by Eqs. 12:5 through 12:7 . Therefore Theorem 12.10 can be easily proved. The circuit Z consists of several two-input two-rail code checkers. According to Theorem 12.6, if these are connected in a cascaded tree structure having r 1 input pairs, meaning I0 ; J0 I1 ; J1 . . . Ir 1 ; Jr 1 , and v; v , then the circuit Z is self-testing for single faults, provided that every input does not have constant value and V v; v can take any value in f0; 1g during normal operation.