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TABLE 8.1 Decoder Gate Amount for 4-Bit Burst Error-Correcting Codes Decoder components Syndrome generator Syndrome decoder Error corrector Errordetector Total
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Source : [UMAN05]. 2005 IEEE.
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K 32 249 535 90 7 881
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K 64 492 1,000 157 8 1,657
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K 128 927 1,740 270 10 2,947
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Here m d N z = R z e, and T denotes the R R companion matrix corresponding to the generator polynomial of C. Proof Suppose that the received word v is corrupted by the error pattern E 2 GF 2R f0g at the j-th frame of the received word. Then S E Tj R l 1 . Therefore E S Tl j R l 1 holds, as required. Now, assume that S Tl w R l 1 Ey , where Ey 2 GF 2R f0g represents a correctable l-bit burst error pattern for some 0 w m 1. Then S Ey Tw R l 1 , that is E Tj R l 1 Ey Tw R l 1 : 8:5
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No l-bit burst error patterns are included in two frames when the received word is divided by m d N z = R z e R-bit frames where adjacent frames overlap by exactly l 1 bits. Therefore, since the code is l-bit burst error correcting, Eq. (8.5) implies j w. However, then E Ey because T is a nonsingular matrix. This completes the proof. Q.E.D. Table 8.1 shows the hardware complexity of the parallel decoding circuit for the 4-bit burst error correcting code that is generated by g x x11 1 x4 x 1 . The codes considered in this table are shortened quasi-cyclic codes of the original (165, 150) code with information lengths K equal to 32, 64, and 128 bits. In this table, a 4-input AND / OR gate is counted as 1 gate and a 2-input XOR (exclusive-OR) gate as 1:5 gates.
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8.3 TRANSIENT BEHAVIOR OF PARALLEL ENCODING / DECODING CIRCUITS OF ERROR CONTROL CODES The relation between the transient behavior (i.e., glitches) of the encoding / decoding circuit and the H matrix construction of an error control code (ECC) has not been addressed before. In the parallel encoding and decoding circuits of error correcting codes, glitches are known to consume extra power and induce simultaneous switching noise [LO05]. It is shown in this section that the probability of a given number of glitches that may accumulate in the encoding / decoding circuit exhibits a Gaussian-like distribution. An estimation methodology was developed so that the transient behavior of an ECC for very large word length can be predicted. As a result the principle of minimum-weight & equal-weight-row construction of H matrix (de ned in Subsection 3.1.1) is demonstrated to be the best design strategy.
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For high-speed transfer of data, parallel encoding / decoding of the error control codes is essential. However, parallel decoding circuits can be very bulky and they constitute primarily from exclusive-OR (XOR) circuits. For example, for a 128-bit information length, a 12-bit burst error correcting code, such as a Fire code, will need about 2,000 to 5,000 logic gates in its parallel decoding circuit, as shown in Subsection 8.1.4. Most of these logic gates, around 80% of them, are XOR gates. As the advent of system-on-chip (SoC), these parallel decoding circuits are an integrated part of a system fabricated along side other circuits and subsystems. Hence the transient behavior (i.e., glitches) of these parallel decoding circuits need to be carefully analyzed. We use the term transient behavior to describe the circuit activities between the insertion of inputs to the nal stabilization of the circuit outputs. Exclusive-OR (i.e., XOR) is a hazardous Boolean function such that its tendency to produce glitches is inherent to the function itself. In other words, there is no way to avoid glitches in the XOR circuits. A glitch is a temporary and unwanted logic state occurs at the circuit output. Often a glitch will not complete a full logic swing and thus may not have impact if the circuit at the next stage is not fast enough to respond. However, as the circuit speed increases, even a halfswing glitch may induce some response at the subsequent circuit. This motivates us to perform in-depth analysis of the transient behavior of the encoding and decoding circuits of the error control codes. Besides creating a dif cult situation for the timing of logic designs [LAVA93, BENI00], glitches in general will consume extra energy [MEHT95, ROY99, BENI00, GHOS04] and elevate the simultaneous switching noise (SSN) [CHEN97, PARR01, TANG02, ROSS04]. As demonstrated in [TANG02], a power bus noise is tied to the total number of switching activities accumulated at any given time. Because glitches cause extra switching activities, they intensify the power bus noise problem. So the total number of glitches is directly proportional to the degree of impact at any given time. The increase of power bus noise will in fact add circuit delays [JIAN00, BAI01]. Until recently the transient behavior of the encoding / decoding circuits of error control codes had rarely been studied. In one recent study [ROSS04], the SSN was analyzed for the Hamming encoded bus. This work concentrates on how the added check bits, to be carried by the additional wires of the bus, can enlarge the SSN problem. In another recent work [GHOS04], the memory traces of benchmark programs are used to determine the probability of transient behavior in each memory bit or pair. Such information is then used to select the H matrix in Hsiao s odd-weight-column SEC-DED code such that the power consumption can be minimized. This is essentially the extension of the idea of [ZHOU00], where the switching activities can be reduced in an XOR circuit if the probability of transient in individual input bit is known. The XOR circuits in a parallel decoding circuit usually have large number of inputs and are typically formed as an XOR tree. The glitches will not only be generated by any XOR gate but will also propagate along the sensitized path to the primary output. The most devastating effect is that the glitches will accumulate in succeeding stages of propagation. The impact to the power bus, in the form of energy consumption or the causes for simultaneous switching noise, is all the glitches accumulated at every stage of the XOR tree. Modern-day SoC s are extremely dense with tens and even hundreds of millions of transistors. The simultaneous switching of so many transistors contributes to the problem
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