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(p+1) by (p+1) digit carry save multiplier
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u(1 .. 2.p)
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is equivalent to u( (p 2), (p 3), . . . , 2:p) v( (p 2), (p 3), . . . , 2:p) (B p 1 1) (B p 1 1) mod B p 1 , where B p 1 1 (B 1, B 1, . . . , B 1): First encode the result of (16.30) in stored-carry form, that is, u( (p 2), (p 3), . . . , 2:p) v( (p 2), (p 3), . . . , 2:p) (B p 1 1) s( (p 2), (p 3), . . . , 2:p) c( (p 2), (p 3), . . . , 2:p): Relation (16.30) is equivalent to s( (p 2), (p 3), . . . , 2:p) c( (p 2), (p 3), . . . , 2:p) (B 1, B 1, . . . , B 1), and the preceding relation only holds if, for every position i, the sum s(i) c(i) is equal to B 2 1. Thus the sticky digit is equal to 0 if, and only if, s(i) c(i) B 1, 8i in { (p 2), (p 3), . . . , 2:p}: (16:30)
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The corresponding circuit is shown in Figure 16.8. The comp block works as follows: if a b B 1 then comp(a, b) 1; else comp(a, b) 0: If B 2 the comp circuit is a 2-input XOR gate.
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DIVIDER
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A basic divider deduced from algorithm 16.6 is shown in Figure 16.9. The inputs of the ( p 1)-digit divider are s1/B and s2 (Comment 6.1), so that the dividend is smaller than the divisor. The precision is chosen equal to p 3 digits. Thus (see Section 6.1) the outputs quotient and remainder satisfy the relation (s1 =B):B p 3 s2 :q r, where r , s2 ,
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16.7 DIVIDER
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u( (p+2) .. 2.p) v( (p+2) .. 2.p) (B 1, B 1, ... , B 1)
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c in = 0
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that is, s1 =s2 q:B ( p 2) (r=s2 ):B ( p 2) where (r=s2 ):B ( p 2) , B ( p 2) :
The sticky digit is equal to 1 if r . 0 and to 0 if r 0. The nal approximation of the exact result is quotient q:B p 2 sticky digit: B p 3 : Example 16.9 (Complete VHDL code available.) Generate the VHDL model of a generic oating-point divider. It is made up of three blocks: 1. Division. This block includes the (p 2)-digit divider, the subtractor, the xor gate, and the sticky digit generation circuit. Any type of divider can be used ( 13). In this model a modi ed (dividend s1/B) restoring divider has been used:
entity division is port ( s1, s2: in digit_vector(0 downto -p); sign1, sign2: in std_logic; e1, e2: in integer;
s1/B 0 s2 e1 e2
FLOATING-POINT UNIT
sign1 sign2
(p+1) digit divider q 0 .. (p+2) r p .. 0
subtractor
sign
sticky digit generation quotient( (p+3))
quotient(0 .. (p+3))
quotient(0)
> 0
s e rounding new_s new_e
Divider.
s: out digit_vector(0 downto -(p+3)); sign: out std_logic; e: out integer ); end division; architecture circuit of division is component modif_div_rest_baseB...end component; ... end circuit;
16.7 DIVIDER
2. Normalization. This circuit multiplies the quotient by B, and decreases the exponent accordingly, if the quotient is smaller than 1:
entity normalization is port ( e: in natural; s: in digit_vector(0 downto -(p+3)); new_s: out digit_vector(0 downto -(p+3)); new_e: out natural ); end normalization; architecture rtl of normalization is signal quotient_by_B: digit_vector(0 downto -(p+3)); begin multiply_by_B: for i in -(p+2) to 0 generate quotient_by_B(i)<=s(i-1); end generate; quotient_by_B(-(p+3))<=0; new_s<=quotient_by_B when s(0)=0 else s; new_e<=e-1 when s(0)=0 else e; end rtl;
3. Rounding. The rounding circuit is the same as before, or even simpler (it is not necessary to normalize after rounding):
entity rounding is port ( s: in digit_vector(0 downto -(p+3)); e: in natural; new_s: out digit_vector(0 downto -p); new_e: out natural ); end rounding;
It remains to assemble the three parts:
entity fp_divider is port ( sign1, sign2: in std_logic; e1, e2: in integer; s1, s2: in digit_vector(0 downto -p); sign: out std_logic; e: out natural; s: out digit_vector(0 downto -p) ); end fp_divider;