CIRCUITS FOR FINITE FIELD OPERATIONS in .NET framework

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CIRCUITS FOR FINITE FIELD OPERATIONS
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This chapter deals with the synthesis of circuits implementing the main nite eld operations: addition, subtraction, product, exponentiation, and inversion. The reason why these operations should be implemented in hardware, instead of just being programmed for some target microprocessor, is the reduction of the computation time. This is particularly true in the case of computer and communications systems including the execution of cryptographic algorithms for security purposes: they use very long operands so that their software-only execution time could become prohibitively long for some real-time applications. An ef cient solution is the development of speci c circuits (coprocessors) executing the most time-consuming operations. OPERATIONS IN Zm Adders and Subtractors
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15.1 15.1.1
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The structure of a base-B modulo m adder is shown in Figure 15.1. It is based on Algorithm 8.2. Its cost is equal to Cmod-adder (n) 2:Cadder (n) n:Cmux2-1:
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Synthesis of Arithmetic Circuits: FPGA, ASIC, and Embedded Systems By Jean-Pierre Deschamps, Gery J. A. Bioul, and Gustavo D. Sutter Copyright # 2006 John Wiley & Sons, Inc.
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(15:1)
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CIRCUITS FOR FINITE FIELD OPERATIONS
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Bn m
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n-digit adder z1
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c2 z1 c1 c2 0
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n-digit adder z2 1
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Modulo m adder.
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If every adder is a ripple-carry adder made up of full-adder cells, then its computation time is equal to Tmod-adder (n) (n 1):TFA Tmux : (15:2)
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The structure of a modulo m subtractor is shown in Figure 15.2. It is based on Algorithm 8.4. Its cost and computation time are practically the same as in the case of the modulo m adder. Cmod-subtractor (n) 2:Cadder (n) n:Cmux2 1 : (15:3)
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If every n-digit adder is a ripple-carry adder made up of full-adder cells, then its computation time is equal to Tmod-subtractor (n) (n 1):TFA Tmux : (15:4)
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Example 15.1 (Complete VHDL source code available.) Generate VHDL models of binary (B 2) modulo m adders and subtractors:
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entity mod_adder is port ( x, y: in std_logic_vector(n-1 downto 0);
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15.1 OPERATIONS IN Zm
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x Bn y m
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n-digit adder z1
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n-digit adder z1 1 z2 0
Modulo m subtractor.
z: out std_logic_vector(n-1 downto 0) ); end mod_adder; architecture circuit of mod_adder is signal z1, z2: std_logic_vector(n-1 downto 0); signal c1, c2: std_logic; signal long_x, long_y, long_result1, long_z1, minus_m, long_result2: std_logic_vector(n downto 0); begin long_x<= 0 &x; long_y<= 0 &y; long_result1<=long_x+long_y; c1<=long_result1(n); z1<=long_result1(n-1 downto 0); long_z1<= 0 &z1; minus_m<=conv_std_logic_vector((2**n)-m, n+1); long_result2<=long_z1+minus_m; c2<=long_result2(n); z2<=long_result2(n-1 downto 0); z<=z1 when (c1 or c2)= 0 else z2; end circuit; entity mod_subtractor is port ( x, y: in std_logic_vector(n-1 downto 0);
CIRCUITS FOR FINITE FIELD OPERATIONS
z: out std_logic_vector(n-1 downto 0) ); end mod_subtractor; architecture circuit of mod_subtractor is signal z1, z2, inv_y: std_logic_vector(n-1 downto 0); signal c1: std_logic; signal long_x, long_inv_y, long_result1: std_logic_vector(n downto 0); begin long_x<= 0 &x; inversion: for i in 0 to n-1 generate inv_y(i)<=not(y(i)); end generate; long_inv_y<= 0 &inv_y; long_result1<=long_x+long_inv_y+ 1 ; c1<=long_result1(n); z1<=long_result1(n-1 downto 0); z2<=z1+conv_std_logic_vector(m, n); z<=z1 when c1= 1 else z2; end circuit;
Multiplication
15.1.2.1 Multiply and Reduce A rst multiplier structure is shown in Figure 15.3. It is based on Algorithm 8.5. As regards the division, observe that the divider is greater than the dividend ( p x.y ,m.m ,m.Bn). Furthermore, it can be assumed that m ! Bm21; in the contrary case all numbers could be
x y m.Bn
multiplier p(2.n 1:0)
(q(n 1:0))
divider
Multiply and reduce algorithm implementation.
15.1 OPERATIONS IN Zm
represented with one digit less. The cost and computation time are equal to Cmultiply-reduce (n) Cmultiplier (n, n) Cdivider (2:n, n), Tmultiply-reduce (n) Tmultiplier (n, n) Tdivider (2:n, n): As regards the computation time observed, if an SRT divider (see 13, Section 13.2.3) is used, the total computation time is a linear function of n. 15.1.2.2 Shift and Add Another multiplier structure can be deduced from Algorithm 8.6. It s an iterative circuit whose basic cell is shown in Figure 15.4. The total cost and computation time are equal to Cshift-add (n) n:(Cmultiplier (n, 1) Cadder (n 1) Cdivider (n 2, 2)), Tshift-add (n) n:(Tmultiplier (n,1) Tadder (n 1) Tdivider (n 2, 2)): In base B 2, Algorithm 8.9 can be used. The corresponding iterative circuit is shown in Figure 15.5. Observe that, in Figure 15.5b, p1 2.p, where 0 p , m, such that 0 p1 , 2.m; p2 p1 2 w, where w m or w m 2 y, with 0 y , m, so that 2m p2 , 2.m; p3 p2 2 m if 0 p2 , 2.m, so that 2m p3 , m; p3 p2 m if 2m p2 , 0, so that 0 p3 , m; conclusion: 2m p3 , m. Thus p2 is an (n 2)-bit number and p3 an (n 1)-bit number.
p(n i) y x(n 1 i)