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<-- clock <-- stage2IsStalled <-- srcProcessorReset
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FeedbackDRegisterWith1Input #(32, 5, 0, 0) IR2 ( clock, stage2IsStalled, fromStage1_IR, intoStage2_IR, srcProcessorReset, 32 hF0000000); FeedbackDRegisterWith1Input #(32, 5, 0, 0) PC2 ( clock, stage2IsStalled, fromStage1_PC, intoStage2_PC, srcProcessorReset, 32 b0); FeedbackDRegisterWith1Input #(32, 5, 0, 0) NextPC2 ( clock, stage2IsStalled, fromStage1_NextPC,
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Appendix B
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intoStage2_NextPC, srcProcessorReset, 32 b0); // // // // // // // // // // // // // // // // // // // Module: Stage2 Description: Instruction Decode and Operand Read Inputs from Stage1 to Stage2: inputPC <-- intoStage2_PC inputIR <-- intoStage2_IR inputNextPC <-- intoStage2_NextPC Outputs from Stage2 to Stage3: outputPC --> outputIR --> outputDecodedIR --> outputX --> outputY --> outputMD --> outputIsRegisterWrite -->
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// outputRa // // Outputs from Stage2 to Stage1 and PC register: // outputBranchIsTaken --> fromStage2_ BranchIsTaken // outputNextPC --> fromStage2_NextPC // // Output to indicate that Stage2 current sees stop instruction: // outputIsStop --> fromStage2_IsStop // // Interface with Register File: // ra --> ra // contentsRaFromRegisterFile <-- contentsRaFrom RegisterFile // rb --> rb // contentsRbFromRegisterFile <-- contentsRbFrom RegisterFile // rc --> rc // contentsRcFromRegisterFile <-- contentsRcFrom RegisterFile // // Interface with Stage3 for forwarding: // isRegisterWriteInStage3 <-- isRegisterWrite InStage3
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fromStage2_PC fromStage2_IR fromStage2_DecodedIR fromStage2_X fromStage2_Y fromStage2_MD fromStage2_ IsRegisterWrite --> fromStage2_Ra
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Appendix B // // // raInStage3 <-- raInStage3 contentsRaFromStage3 <-- contentsRaFromStage3 contentsRaFromStage3Ready <-- contentsRaFromStage3 Ready
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// // Interface with Stage4 for forwarding: // isRegisterWriteInStage4 <-- isRegisterWrite InStage4 // raInStage4 <-- raInStage4 // contentsRaFromStage4 <-- contentsRaFromStage4 // contentsRaFromStage4Ready <-- contentsRaFromStage 4Ready // // Interface with Stage5 for forwarding: // isRegisterWriteInStage5 <-- isRegisterWrite InStage5 // raInStage5 <-- raInStage5 // contentsRaFromStage5 <-- contentsRaFromStage5 // contentsRaFromStage5Ready <-- contentsRaFromStage 5Ready // // Output to Stage1 to indicate stall condition: // stage2IsStalled --> stage2IsStalled // // Selectively enable forwarding for experimentation: // enableForwarding <-- enableForwarding // Stage2 stage2 (intoStage2_PC, intoStage2_IR, intoStage2_NextPC, fromStage2_PC, fromStage2_IR, fromStage2_DecodedIR, fromStage2_X, fromStage2_Y, fromStage2_MD, fromStage2_IsRegisterWrite, fromStage2_Ra, fromStage2_BranchIsTaken, fromStage2_NextPC, fromStage2_IsStop, ra, contentsRaFromRegisterFile, rb, contentsRbFromRegisterFile, rc, contentsRcFromRegisterFile, isRegisterWriteInStage3,
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Appendix B raInStage3, contentsRaFromStage3, contentsRaFromStage3Ready, isRegisterWriteInStage4, raInStage4, contentsRaFromStage4, contentsRaFromStage4Ready, isRegisterWriteInStage5, raInStage5, contentsRaFromStage5, contentsRaFromStage5Ready, stage2IsStalled, enableForwarding); // // // // // // // // // // // // // // // Module: DRegister
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Description: Registers for interface between stage 2 and stage 3 Inputs: clk d reset resetValue Outputs: q
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<-- clock <-- srcProcessorReset
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DRegister #(32, 5, 0, 0) PC3 ( clock, fromStage2_PC, intoStage3_PC, srcProcessorReset, 32 b0); DRegister #(32, 5, 0, 0) IR3 ( clock, fromStage2_IR, intoStage3_IR, srcProcessorReset, 32 hF0000000); DRegister #(32, 5, 0, 0) DecodedIR3 ( clock, fromStage2_DecodedIR, intoStage3_DecodedIR, srcProcessorReset, 32 h40000000); DRegister #(32, 5, 0, 0) X3 ( clock, fromStage2_X,
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Appendix B intoStage3_X, srcProcessorReset, 32 b0); DRegister #(32, 5, 0, 0) Y3 ( clock, fromStage2_Y, intoStage3_Y, srcProcessorReset, 32 b0);
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DRegister #(32, 5, 0, 0) MD3 ( clock, fromStage2_MD, intoStage3_MD, srcProcessorReset, 32 b0); DRegister #(1, 5, 0, 0) IsRegisterWrite3 ( clock, fromStage2_IsRegisterWrite, intoStage3_IsRegisterWrite, srcProcessorReset, 1 b0); DRegister #(5, 5, 0, 0) Ra3 ( clock, fromStage2_Ra, intoStage3_Ra, srcProcessorReset, 5 b0);
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// // // // // // // // // // // // // // // //
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Module: FeedbackDRegisterWith1Input Description: Registers for interface between stage Inputs: clk shouldHold d reset resetValue Outputs: q
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1 and stage 2
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clock hasDecodedStop fromStage2_IsStop srcProcessorReset
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--> hasDecodedStop
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FeedbackDRegisterWith1Input #(1, 5, 0, 0) HasDecodedStop ( clock, hasDecodedStop, fromStage2_IsStop,
Appendix B hasDecodedStop, srcProcessorReset, 1 b0); // // Module: Stage3 // // Description: // ALU operations // // Inputs from Stage2: // inputPC // inputIR // inputDecodedIR // inputX // inputY // inputMD // inputIsRegisterWrite // inputRa // // Outputs to Stage3: // outputPC // outputIR // outputDecodedIR // outputZ // outputMD // outputIsRegisterWrite
<-<-<-<-<-<-<--
intoStage3_PC intoStage3_IR intoStage3_DecodedIR intoStage3_X intoStage3_Y intoStage3_MD intoStage3_IsRegister Write <-- intoStage3_Ra
--> --> --> --> --> -->
// outputRa // // Interface with Stage2 for forwarding: // isRegisterWrite --> isRegisterWriteInStage3 // ra --> raInStage3 // contentsRa --> contentsRaFromStage3 // contentsRaReady --> contentsRaFromStage3Ready // Stage3 stage3 (intoStage3_PC, intoStage3_IR, intoStage3_DecodedIR, intoStage3_X, intoStage3_Y, intoStage3_MD, intoStage3_IsRegisterWrite, intoStage3_Ra, fromStage3_PC, fromStage3_IR, fromStage3_DecodedIR,
fromStage3_PC fromStage3_IR fromStage3_DecodedIR fromStage3_Z fromStage3_MD fromStage3_IsRegister Write --> fromStage3_Ra
Appendix B fromStage3_Z, fromStage3_MD, fromStage3_IsRegisterWrite, fromStage3_Ra, isRegisterWriteInStage3, raInStage3, contentsRaFromStage3, contentsRaFromStage3Ready); // // // // // // // // // // // // // // // Module: DRegister Description: Registers for interface between stage 3 and stage 4 Inputs: clk d reset resetValue Outputs: q