Setting a pack factor can help to determine the true utilization. in Visual Studio .NET

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Setting a pack factor can help to determine the true utilization.
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In other words, an FPGA that reports 60% utilization may have much more than 40% more logic resources available (ignoring the routability issues as utilization approaches 100% of course). To estimate true utilization and headroom in the design, the pack factor can be reduced until the design cannot be properly routed.
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16.8 Register Ordering
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16.7 MAPPING LOGIC INTO RAM
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The major players in the high-end FPGA world are SRAM based, which means that logic functions are coded into LUTs. These LUTs are small SRAM cells distributed across the FPGA and available for general logic implementation. It would seem that a natural extension of this would be to implement logic in the larger dedicated RAM blocks (the ones actually used like RAM), particularly when utilization is running low. Although this may make sense conceptually, the problem associated with this is performance. The small distributed RAM cells will have very small delays, and logic will propagate through these LUTs very quickly and ef ciently relative to other logic elements. The larger RAM blocks, on the other hand, will have much larger delays associated with them and will subsequently create a very slow implementation. In general, it is not wise to rely on logic that is packed into dedicated RAM blocks. Only as a last resort in an extremely high density and slow design would this be useful.
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16.8 REGISTER ORDERING
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Register ordering is a method used by the placement tool to group adjacent bits of a multibit register into a single logic element. Most cell-based logic elements have more than one ip- op, and thus by placing adjacent bits together the timing can be optimized as shown in Figure 16.11.
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Sequential bits are ordered.
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16 Place and Route Optimization
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Performance reduction with register ordering.
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The problem that arises with register ordering is that it may prevent a group of registers that have added pipelining for route balancing to be grouped together. This will prevent the additional registers from dividing the routing delay as originally intended. Consider the delay balancing register used above when packing registers into I/O buffers. As can be seen from Figure 16.12, the bene t of the pipelined register has been eliminated due to the fact that it has been placed adjacent to its driver.
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Register ordering should not be used when extra ip- ops have been added to divide routing delay.
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16.9 PLACEMENT SEED
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Designers typically do not like the concept that there may be a certain degree of randomness in their design ow or implementation tools. However, it is important to note that a placement for a given design with a set of constraints is not entirely deterministic. In other words, there is no single optimal placement for any given design; at least, not one that can be easily determined by today s technology prior to the placement process itself. In fact, as shown in Figure 16.13 this is not an obvious problem at all, even for an automated placer, to determine the optimal starting point for the placement process. Thus, the placement tool needs to be seeded similar to a process for random number generation. The exact de nition of a seed is a bit abstracted from the standpoint of the designer, but for useful purposes, different seeds essentially provide the placer with slightly different starting points by which the rest of the placement process branches. This is illustrated in Figure 16.14. Some vendors extend this beyond simply the initialization to other random parameters of the placement process such as relative weighting of the various constraints, desirable placement distances, and estimates for routing congestion. Xilinx calls this the placement cost table, which affects the various placement parameters, but abstracts this to an integer (1, 2, 3, etc.). Each integer corresponds with a different set of initial conditions and placement parameters, but because of the low level complexity, it is abstracted to a single number and the actual functionality is hidden from the parameter table.
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