Synthesis Optimization in Visual Studio .NET

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Synthesis Optimization
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Most implementation tools for FPGA synthesis provide the designer with
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dozens of optimization options. The main problem most designers run into is that it is not clear what these options do exactly and more importantly how these can be used to actually optimize a design. Most designers never fully understand these optimization options, and after spending hours, days, or weeks playing around with the endless combinations, they nd a formula that seems to give them the best results. After having gone down this road, few designers ever approach these optimizations beyond the formulas that have worked for them in the past. Thus, most optimizations go unused due to a fundamental lack of understanding and the dif culty in developing a full arsenal of heuristics. This chapter describes the most important aspects of synthesis optimization at the implementation level based on tried-and-true real-world experience and will provide practical heuristics along the way that can be immediately leveraged by the reader. During the course of this chapter, we will discuss the following topics in detail:
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. . .
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Trade-offs with speed versus area. Resource sharing for area optimization. Pipelining, retiming, and register balancing for performance optimization. The effect of reset on register balancing Handling resynchronization registers
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Optimizing FSMs. Handling black boxes. Physical synthesis for performance.
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Advanced FPGA Design. By Steve Kilts Copyright # 2007 John Wiley & Sons, Inc.
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14 Synthesis Optimization
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14.1 SPEED VERSUS AREA
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Most synthesis tools provide switches that allow the designer to target speed versus area optimization. This seems like a no-brainer: If you want it to run faster, choose speed. If you want it to be smaller, choose area. This switch is misleading because it is a generalization of certain algorithms that can sometimes produce the opposite result (i.e., the design becomes slower after telling it to go faster). Before we understand why this happens, we must rst understand what speed and area optimizations actually do to our design. At the synthesis level, speed and area optimizations determine the logic topology that will be used to implement our RTL. At this level of abstraction, there is little known about the physical nature of the FPGA. Speci c to this discussion, this would relate to the interconnect delay based on the place and route. Synthesis tools use what are called wire load models, which are statistical estimates of interconnect delay based on various criteria of the design. In an ASIC, this is accessible to the designer, but with FPGA design this is hidden behind the scenes. This is where the synthesis tool comes up with its estimates, which are often signi cantly different from the end result. Due to this lack of knowledge from the back end, synthesis tools will primarily execute gate-level optimizations. In high-end FPGA design tools, there exists a ow called placement-based synthesis to help close this loop, and this is discussed at the end of the chapter. The synthesis-based gate-level optimizations will include things like statemachine encoding, parallel versus staggered muxing, logic duplication, and so on. As a general rule of thumb (although certainly not always true), faster circuits require more parallelism, which equates with a larger circuit. Therein lies the basic conceptual trade-off between speed and area: Faster circuits require more parallelism and an increase in area. Because of the second-order effects from FPGA layout, however, this does not always work out as expected. It isn t until place and route is completed before the tool really knows how congested the device is or the dif culty in the place and route process. At this point in the ow, a particular logic topology has already been committed to by the synthesis tool. Thus, if an optimization effort was set to speed at the synthesis level and the back-end tool nds that the device is overly congested, it must still attempt to place and route all the extra logic. When the device is congested, the tool will have no choice but to place the components wherever they will t and will therefore introduce long delays due to the suboptimal routes. Because of the fact that designers will often use the smallest FPGA possible for economic reasons, this situation occurs very frequently. This leads to the general heuristic:
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As the resource utilization approaches 100%, a speed optimization at the synthesis level may not always produce a faster design. In fact, an area optimization can actually result in a faster design.
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The plot in Figure 14.1 represents actual timing data from a RISC microprocessor implemented in a Virtex-II FPGA relative to the timing constraint.
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