HARDWARE DIVISION

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Division operations have always caused headaches for digital logic designers. Unlike addition, subtraction, or multiplication, there is no simple logic operation that will generate a quotient. Among other subtle dif culties, division differs from the other arithmetic operations in that xed-point operations do not produce a nite and predictable xed-point result. There are, however, a number of ways to deal with this issue. The simplicity of the solution will be entirely application dependent, but for the sake of discussion we will begin with the simple solutions requiring speci c constraints and then move on to general solutions.

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Multiply and Shift

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The multiply and shift method is the simplest solution to the division problem and is essentially equivalent to multiplying by the inverse of the divisor. This solution leverages the basic property of binary numbers that a shift to the least-signi cant position (a right shift in most HDL representations) will result in a divide-by-two. If an 8-bit register has a xed point at bit 4 and contains the integer value of 3, the register will have the representation shown in Figure 8.1. With the xed-point representation de ned earlier, the number represented in Figure 8.1 is equivalent to: 21 20 3. If we divide by 2, we can perform a right shift by 1 as shown in Figure 8.2. The register of Figure 8.2 now holds the value 20 221 1.5. A simple multiply and shift technique assumes the divisor is xed to some constant and de nes the divide operation as a multiply followed by a divide by some power of 2. For instance, a divide by 7 could be approximated by a multiplication by 73 followed by a divide by 512 (implemented with a 9-bit right shift). The result is a divide by 7.013 . . . . Greater precision can be achieved by increasing the power of 2 and increasing the multiplication factor appropriately. As mentioned previously, this is essentially equivalent to inverting the divisor and multiplying. Speci cally, the divisor is inverted and converted to a unique xed-point number ( xed point at the ninth bit in the above example) and then converted back to the original xed-point format. This technique works well for highspeed divisions by constant factors or for applications where only a few bits of precision are required (many bits of precision require large multiply operations).

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The multiply and shift method is an easy way to perform division but can only be used when the divisor is represented in a speci c form.

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It should be noted that to represent the fractional number properly, some other device such as an external microprocessor will need to provide an initial

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Figure 8.1 Fixed-point representation of 3.

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Figure 8.2 Fixed-point representation of 1.5.

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8.1 Hardware Division

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inversion. If an external device is de ning the divisor, this method can work well. If the divisor is determined by some other logic and the design does not have the luxury of this representation, then other methods will be required as described in the following sections.

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Iterative Division

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The division algorithm discussed in this section is an example of an algorithm that falls into a class of digit recurrence methods. Iterative methods typically refer to successive approximation methods (discussed in the next section), but for consistency with other chapters, we will refer to this as an iterative method as it maps to similar iterative methods used for compact implementations of other functions. Iterative division works much like long division with decimal numbers did in elementary school. One of the advantages in using binary numbers, however, comes from the fact that certain optimizations can be made in the division process. Take the following long division example with the binary representations of 2 divided by 3 as shown in Figure 8.3. The divider for a xed-point number can be architected as shown in Figure 8.4 with a comparator and a subtraction unit. With this architecture, the dividend is normalized to a xed-point value that is necessarily smaller than twice the divisor. By doing this, every subsequent shift operation will produce a new partial quotient that must be less than twice the divisor. This means that the divisor will go into the partial quotient 1 or 0 times. If the divisor is less than or equal to the partial dividend for the current iteration, a logic-1 is shifted into the quotient register, otherwise, a logic-0 is shifted in and the partial dividend is shifted left by 1. After the necessary number of iterations to achieve the desired precision, the output is postnormalized to shift the data to the proper xed-point location (undo the prenormalization).

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