Maintaining real-time performance in Visual Studio .NET

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Maintaining real-time performance
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This section explores some techniques for writing code with real-time performance requirements and also for writing code that does not compromise the real-time requirements of other code. It also explains some of the limitations of EKA2 for real-time systems.
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18.2.1.1 Task partitioning
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The rst thing you should consider when writing any real-time software is how to partition the desired functionality into separate tasks, according to the deadlines involved. Some of these tasks may run as interrupt service routines, others will run in threads with varying priority levels. You should only do the minimum amount of work needed to meet a deadline at any given priority level. Work that is less urgent should be postponed to lower priority tasks, where it will not hold up more urgent
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activities. This is especially important for tasks which run as ISRs, since these run in preference to threads. Interrupts should always be kept as short as possible. The following table gives a rough guide to the thread priority ranges that would be used for tasks with certain deadlines: Priority 0 1 15 16 16 24 25 26 27 28 31 28 47 Deadline range >100 ms >20 ms 2 20 ms 2 20 ms Null (idle) thread. Normal application priorities. Kernel cleanup activities. System servers ( le server, window server and so on). Media drivers. General device drivers. The default DFC thread (DfcThread()) runs at this priority. Real-time priority Symbian OS user processes. High priority kernel-side threads and personality layer threads. Priorities above 31 are not directly accessible user-side and must be set using a device driver. Nanokernel timer thread. Personality layer threads. Personality layer routines to enable ISRs to wakeup threads. Comments
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48 49 63 IDFC ISR
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2 20 ms 100 s 10 ms 100 s 1 ms 10 s 1 ms
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Threads that run in normal Symbian OS user processes, with priorities of EPriorityForeground or lower, have absolute priorities between 1 and 15. Various Symbian OS servers with high legacy code content, which were not written with real-time performance in mind, inhabit priorities 16 24 and so it is not possible to give any meaningful real-time guarantees for code running at these priorities. At the high end of the spectrum, the deadlines possible at each priority depend on the speed of the hardware and how the base port is written. On very fast hardware it should be possible to service deadlines of 100 s with a priority 63
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kernel thread, provided the base port does not have long ISRs. On slower hardware, tasks with deadlines of 1 ms will need to be ISRs.
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18.2.1.2 Avoid priority inversion
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When choosing a mutual exclusion method for use in software that must meet real-time deadlines, you should take care to minimize the time for which priority inversion exists. The following methods are available:
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1. Lock-free algorithms Lock-free algorithms for updating data structures make use of atomic memory access instructions such as SWP on ARMv5, LDREX/STREX on ARMv6 and locked instructions on IA32. The ARM SWP instruction atomically interchanges the contents of a register with the contents of a memory location. The instruction is atomic with respect to other code running on the same processor (simply by virtue of being a single instruction, so not interruptible between the read and write) and also with respect to accesses by other bus masters. No other bus master in the system can access the memory location referred to in between the read and write part of the SWP. The ARM LDREX and STREX instructions make use of an exclusive access monitor, which on systems with only a single processor is just a single bit hardware ag. The ag is usually clear, or, in ARM s terminology, in the Open Access state. Executing an LDREX instruction loads the contents of a memory location into a register and sets the ag (puts it into the Exclusive Access state). Executing a STREX instruction checks the state of the ag. If it is in the Exclusive Access state, the contents of the register is written into a memory location and a value of 0 is written into the result register. If the ag is in the Open Access state, no memory write occurs and the result register is set to 1. In either case, the ag is reset to the Open Access state by a STREX instruction. The usage of these instructions is illustrated here:
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