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motion, and is done with the intent of improving performance by executing fewer instructions, optimizing register usage, accessing related memory closer together (spatial locality), and / or accessing memory less frequently A compiler must preserve sequential behav ior when moving code, but can reorder things in ways that change the code's behavior when it is run in a multithreaded setting
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2 Modern processors employ instruction level parallelism (ILP) techniques such as pipelining, superscalar execution, and branch prediction to overlap the execution of many instructions The aim is to reduce the total cycle time taken to execute a set of instructions A pair of memory loads from separate locations a and b may exe cute simultaneously in the processor 's instruction pipeline, for instance, and, although a textually preceded b in the original source code, b may be permitted to complete before a This may be legal if the processor believes it is harmless, that is, there is no dependency between the two 3 The computer architectures on which Windows runs employ a hier archy of fast caches to amortize access to main memory Some cache can be shared among processors, while other levels in the hierarchy are not Many processors also employ write buffers that delay stores Although it's convenient to view memory as a big array of values that are read from and written to directly, caches break this model They must be kept globally consistent through a hardware facility called cache coherency Different architectures employ different coherency policies, governing precisely when writes will actually reach main memory and when loads must refresh the local processor cache These factors can cause loads and stores to appear to have executed out of order This hierarchy of transformation can be viewed pictorially in Figure 1 0 1 All three of the above categories will typically be lumped together under the term instruction reordering Most programmers need not be concerned with this But those who are interested in low level concurrent programming routinely need to think about it Three distinct notions of "order" are important to understand
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What Runs Isn't Always What You Wrote As a simple motivating example of what can go wrong due to instruction reordering, let's take a look at the following program Imagine that the two shared variables, x and y, both contain the value 0 at the outset Two threads, to and tI , execute a separate sequence of instructions
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I s i t possible that a b 0 after threads to and tl have both run once Aside from the mind bending nature of this problem, an answer of "yes" at first seems ridiculous We might reason this as follows: if we plot this program's execution on a timescale, either the statement x l or y 1 must execute first; therefore, no matter what instruction is chosen to run next, the read of the written variable will occur later in time, and it should, therefore, see the previously written value The only legal orderings based on this reasoning would be:
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All of these appear to have run in the original program order and all looks well The answer to the original question-can a b 0 occur-is "yes" (more accurately, "possibly") because of instruction reordering The pro gram can be morphed into any permutation of the four instructions, either statically (by the compiler) or dynamically (by the processor or memory system) The program could appear to have been written like this instead (among other possibilities)
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I f that's the code w e had written, surely we'd notice a problem with it! The stores occur after the loads, so it's certainly possible that both threads would see a value of O It is suddenly painfully obvious why the outcome a b 0 is possible: