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CE3 4 A16 5 A19 6
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E1 E2 E3 74HC138
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Eight I/O lines decoded in CE space
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The decoder chip used in this circuit, a 74HC138, provides a one of eight decode If the decoder s three enable lines (E1, E2, and E3) are in their active states (low, low, and high, respectively), the three address lines (A5, A6, and A7) are used to provide eight (23) distinct input values The state of these three address lines causes exactly one of the decoder s eight outputs to be in its active low state, as shown in Table 82 Because the least signi cant ve address lines are not used in this circuit for decoding purposes, each output decodes a 32-byte (2 5) range in memory7 In this example, we only use one of these outputs (Y0) for selecting the latch and buffer used for output and input, respectively
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Parallel I/O Examples Table 82
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A 0 1 0 1 0 1 0 1 B 0 0 1 1 0 0 1 1
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74HC138 truth table
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C 0 0 0 0 1 1 1 1 Y0 0 1 1 1 1 1 1 1 Y1 1 0 1 1 1 1 1 1 Y2 1 1 0 1 1 1 1 1 Y3 1 1 1 0 1 1 1 1 Y4 1 1 1 1 0 1 1 1 Y5 1 1 1 1 1 0 1 1 Y6 1 1 1 1 1 1 0 1 Y7 1 1 1 1 1 1 1 0
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The signals CE3, A16, and A19 drive the decoder s enable lines By studying the chip enable and all of the address lines used by the decoder, we can determine an address that can be used to access the additional I/O lines using a DataPort object DataPort operates with 32-bit addresses For the purposes of this discussion, we ll refer to the address bits as a0 through a31, where a0 is the least significant address bit and a31 is the most signi cant address bit Note that we use a lowercase a to avoid confusion with the address bus signal names (A0 A19) Because the circuit is decoded in CE space, we know from the memory map shown in Figure 82 that the highest possible address is 0x3FFFFF This means that a22 a31 must all be 0 Bits a20 and a21 are determined by our choice of chip select signals, as shown in Table 83 Table 83
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CE0 0 1
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Chip enable to high-order address bit mapping
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CE1 1 0 CE2 1 1 CE3 1 1 a20 0 1 a21 0 0
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continues
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7 This decode logic is compatible with, but not identical to, the decode used in the E series socket boards The E series socket board schematics are included in the accompanying CD and can also be found online at http://wwwibuttoncom/TINI/developers/ indexhtml
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Parallel I/O
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Table 83
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CE0 1 1
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Chip enable to high-order address bit mapping (continued)
CE1 1 1 CE2 0 1 CE3 1 0 a20 0 1 a21 1 1
Because we re using CE3, both a20 and a21 are 1 The lower 20 bits of the address (a0 through a19) are determined simply by a 1 to 1 mapping of the 20address bus signals (A0 A19) The states of the address lines that are not used in the decode are irrelevant, so we ll refer to them as don t care bits (or lines) Figure 84 shows the combination of the different address elds The bit positions marked with an X are don t care bits
a31 > a22 0000000000 X => don't care a21 1 a20 1 a19 1 a18 X a17 X a16 X a15 >a8 XXXXXXXX a7 0 a6 0 a5 0 a4 > a0 XXXXX
Constructing the DataPort address
Note that because a0 a4 are all don t cares, all addresses in the range [0x380000 0x3801F] will enable bus access to the I/O circuitry Also, because there are higher-order don t care bits in the address, there are many such 32-byte address ranges To select a speci c address, we ll simply set all of the don t care bits to 0, resulting in an address of 0x380000 While this is not a precise decode, it does ensure that our new I/O circuitry will not con ict with the other devices attached to the microcontroller s bus Speci cally, the decision to require that address line A19 be high and address line A16 be low keeps the new I/O lines out of the way of the Ethernet controller and the real-time clock Now that we ve covered the somewhat tricky subject of decoding a valid address for transferring data to and from the additional I/O lines, the overall operation of the circuit can be described simply During a bus write operation to address 0x380000, both Y0 and WR will be in their active states, causing the contents of the data bus (D0 D7) to be written to the latch s output lines (1Q 8Q) Likewise, during a bus read operation from address 0x380000, both Y0 and PSEN will be in their active states, causing the contents of the buffers s input lines to be transferred onto the data bus The circuit can be tested by connecting IN1 to OUT1, IN2 to OUT2, and so on, producing a simple loopback con guration The ParallelLoopBack test program, shown in Listing 81, creates a DataPort object attached to address