1-Wire Signalling in Java

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1-Wire Signalling
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The extremely simple hardware con guration of a 1-Wire network is shown in Figure 41
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VPUP 1-Wire master Rx Tx 1-Wire chip (slave) Rx 1-Wire chip (slave) Rx 22 K Ohm (T yp)
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Rx = Receive Tx = Transmit
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Tx 100 Ohm MOSFET
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1-Wire network hardware con guration
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1 A thorough treatment of 1-Wire networking is provided at http://wwwibuttoncom/ ibuttons/standardpdf 2 Details on platform support for the Java 1-Wire API can be found at http://wwwibuttoncom/software/1wire/1wire_apihtml
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1-Wire Networking Fundamentals
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1-Wire devices are open drain driven and can therefore only drive the bus low The devices rely on either an external pull-up resistor on the master end of the bus or a pull-up resistor integrated into a dedicated master chip to return the bus to a high state In normal operating conditions the bus is not even driven high by the master There are, however, circumstances when a properly con gured master will actively drive the line high for very brief durations to aid communication over long line lengths Most 1-Wire devices can communicate at two different speeds 3: regular speed and overdrive speed If not explicitly set into the overdrive speed, devices will communicate at regular speed Regular speed results in a maximum data rate of 163 kilobits per second, while overdrive speed results in a maximum data rate of 144 kilobits per second The characteristics of the waveforms at the two different speeds are the same except for the duration There are four distinct signals (or waveforms) generated by the master on the 1-Wire bus 1 2 3 4 Reset sequence Write 0 Write 1 Read data
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The reset sequence is used to return all devices on the bus to a known initial state It consists of a master generated reset pulse followed by a device generated presence pulse The master transmits a reset pulse by driving the bus low for a minimum 480 s at regular speed or 48 s at overdrive speed The master then releases the bus and goes into receive mode The bus is pulled to a high state via the pull-up resistor After detecting the rising edge on the bus, the devices wait 15 to 60 s at regular speed or 2 to 6 s at overdrive speed and then transmit the presence pulse by driving the bus low for a time of 60 to 240 s at regular speed or 8 to 24 s at overdrive speed A reset pulse of 480 s or longer will return any devices communicating at overdrive speed to regular speed The read and write data signals are known as time slots All time slots are initiated by the master driving the bus low for at least 1 s The falling edge of the data line synchronizes the slave devices to the master Each slave device employs a delay circuit that is triggered by this falling edge During write time slots, the delay circuit determines when the devices will sample the bus For a read data time slot, if a 0 is to be transmitted, the delay circuit determines how long the devices will hold the data line low overriding the 1 generated by the master If the data bit is a 1, the device will leave the read data time slot unchanged An important point to make
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3 Some of the older 1-Wire devices are only capable of communication at regular speeds Supported speeds for any device are speci ed in that device s data sheet
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The 1-Wire Net
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here is that any device that transmits a 0 in response to a master initiated read time slot will override or hide any 1 transmitted by any other device Since lows (logical 0s) are actively driven and highs (logical 1s) are soft due to the relatively large pullup resistor between the bus and power, 0s win any contention This point is important in understanding the address discovery process described in Section 413 Note that the master samples the 1-Wire line whether it is transmitting or receiving This means that the application receives the data it transmits This fact can be used by an application as a quick check to ensure that the data it transmitted was not altered by errors such as a momentary short of the 1-Wire line to ground We ll put this to the test in Listing 46 This quick check, however, does not obviate the need to protect 1-Wire data using CRCs (cyclic redundancy checks) as described in Section 45
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