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(a) Prove that the relation below holds for N; N R SbEC-ADbED code: N b 2R 22b 2b: 2b 1
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(b) Show that null space of the following parity-check matrix is an SbEC-ADbED code:
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where H0 is a nonsingular binary matrix with rank 2b, 0 i q 2, q 2b , I is a b b identity matrix, O is a b b zero matrix, and T is a b b companion matrix de ned by the binary primitive polynomial with degree b. Also show that the maximum code length in bits is given by N 2b 2b R=b 2 , where n R=b 2. (c) Take the challenge to design a more ef cient code than the code shown in (b).
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[ARLA84] J. Arlet and W. C. Carter, Implementation and Evaluation of a b; k -Adjacent Error Correcting / Detecting Scheme for Supercomputer Systems, IBM J. Res. Dev., 28 (March 1984): 159 168. [BHAT78] A. K. Bhatt and L. L. Kinney, A High Speed Parallel Encoder / Decoder for b-Adjacent Error-Checking Codes, Proc. 3rd USA Japan Computer Conf. (1978): 203 207. [BISH96] J. W. Bishop, M. J. Campion, T. L. Jeremiah, S. J. Mercier, et al., PowerPC AS A10 64-Bit RISC Microprocessor, IBM J. Res. Dev., 40 (July 1996): 495 505. [BOSS70] D. C. Bossen, b-Adjacent Error Correction, IBM J. Res. Dev., 14 (July 1970): 402 408. [BURT71] H. O. Burton, Some Asymptotically Optimal Burst-Correcting Codes and Their Relation to Single-Error Correcting Reed-Solomon Codes, IEEE Trans. Info. Theory, IT-17 (January 1971): 92 95. [CART74] W. C. Cater, G. B. Leeman Jr., and A. B. Wadia, Practical Length Single-Bit Error Correction / Double-Bit Error Detection Codes for small Values of b, IBM Techn. Dis. Bull., 17 (December 1974): 2174 2176. [CART80] W. C. Carter and A. B. Wadia, Design and Analysis of Codes and Their Self-Checking Circuit Implementations for Correction and Detection of Multiple-b-Adjacent Errors, Dig., 10th IEEE Int. Symp. Fault-Tolerant Computing (October 1980): 35 40. [CHEN83] C. L. Chen, Error-Correcting Codes with Byte Error-Detection Capability, IEEE Trans. Comput., C-32 (July 1983): 615 621. [CHEN86a] C. L. Chen, Byte-Oriented Error-Correcting Codes for Semiconductor Memory Systems, IEEE Trans. Computers, C-35 (July 1986): 646 648. [CHEN86b] C. L. Chen, Error-Correcting Codes for Byte-Organized Memory Systems, IEEE Trans. Info. Theory, IT-32 (March 1986): 181 185.
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CODES FOR HIGH-SPEED MEMORIES II: BYTE ERROR CONTROL CODES
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[CHEN91] C. L. Chen and L.E. Grosbach, Fault-Tolerant Memory Design in the IBM Application System/400TM , Dig. 21th IEEE Int. Symp. Fault-Tolerant Computing (June 1991): 393 400. [CHEN92] C. L. Chen, Symbol Error-Correcting Codes for Computer Memory Systems, IEEE Trans. Comput., 41 (February 1992): 252 256. [DENG87] R. H. Deng and D. J. Costello Jr., Decoding of DBEC-TBED Reed-Solomon Codes, IEEE Trans. Comput., C-36 (November 1987): 1359 1363. [FIRE59] P. Fire, A Class of Multiple-Error-Correcting Binary Codes for Non-Independent Errors, Sylvania Report RSL-E-2, Sylvania Electronic Defense Laboratory, Reconnaissance, Systems Division (1959). [FUJI76] E. Fujiwara, Modularized b-Adjacent Error Correction (in Japanese), Paper of Technical Group, IECE Japan, EC76 19 (1976). [FUJI77a] E. Fujiwara, A Modularized b-Adjacent Error Correction Memory Unit, Trans. IECE Japan, E60 (February 1977): 69 76. [FUJI77b] E. Fujiwara and T. Kawakami, Modularized b-Adjacent Error Correction, Dig., 7th IEEE Int. Symp. Fault-Tolerant Computing (June 1977): 199. [FUJI78] E. Fujiwara, Odd-Weight-Column b-Adjacent Error Correcting Codes, Trans. IECE Japan, E61 (October 1978): 781 787. [FUJI81] E. Fujiwara, Error Correcting Code and Its Application to Digital Systems (in Japanese), PhD Dissertation, Tokyo Institute of Technology (April 1981). [FUJI82] E. Fujiwara and S. Kaneda, Application of Error Correcting Codes for Increasing Computer System Reliability (in Japanese), J. Info. Process. Soc. (IPS) Japan, 23 (April 1982): 292 298. [FUJI90] E. Fujiwara, in H. Imai (ed.), Essentials of Error-Correcting Coding Techniques, Academic Press (1990), ch. 4. [HAMM50] R. W. Hamming, Error Detecting and Error Correcting Codes, Bell Syst. Techn. J., 26 (April 1950): 147 160. [HART72] C. R. P. Hartman and K. K. Tzeng, Generalization of the BCH Bound, Info. Control, 18 (1972): 489 498. [HONG72] S. J. Hong and A. M. Patel, A General Class of Maximal Codes for Computer Applications, IEEE Trans. Comput., C-21 (December 1972): 1322 1331. [HORI83] T. Horiguchi and Y. Sato, A Decoding Method for Reed-Solomon Codes over GF 2m (in Japanese), Trans. IECE Japan, J66-A (January 1983): 97 98. [IMAI79] H. Imai and Y. Kamiyanagi, On Burst-Error-Correcting Codes for Application to Main Memories (in Japanese), Trans. IECE Japan, J62-D (October 1979): 633 640. [ITOH83] H. Itoh and M. Nakamichi, SbEC-DbED Codes Derived from Experiments on a Computer for Semiconductor Memory Systems (in Japanese), Trans. IECE Japan, J66-A (August 1983): 741 748. [JOHJ97] Y. Johji and E. Fujiwara, A Class of Byte Error Control Codes Based on Hierarchical Error Model, Technical Report of IEICE, FTS 96-58 (February 1997). [KANE82] S. Kaneda and E. Fujiwara, Single Byte Error Correcting-Double Byte Error Detecting Codes for Memory Systems, IEEE Trans. Comput., C-31 (July 1982): 596 602. (Also in Dig., 10th Ann. Int. Symp. Fault-Tolerant Computing [October 1980]: 41 46.) [NARA80] Y. Nara, Y. Sohma, and A. Hattori, Error-Correcting and Error-Detecting Systems, US Patent 4214228 (July 22, 1980). [NUMA89] K. Numata, Y. Oowaki, Y. Itoh, et al., New Nibbled-Page Architecture for HighDensity DRAMs, IEEE J. Solid-State Circ., 24 (August 1989): 900 904.
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