SINGLE-BYTE ERROR CORRECTING (SbEC) CODES

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On the other hand, H0 can be given by j 6 H0 4 1 j 2 j a j j a2 j j a3 j j a4 j j a5 j 3 j 7 a6 5 ; j

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where a is a root of p x . From the polynomial p x the following companion matrix and the addition table on GF 23 can be derived: 2 3 1 15 0 0 I T T2 T3 T4 T5 T6 0 0 I T T2 T3 T4 T5 T6 I I 0 T3 T6 T T5 T4 T2 T T2 T3 T4 T5 T6

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0 T 41 0

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T T2 T3 T6 0 T4 4 T 0 I T5 2 T T T6 T3 T5 I

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T3 T4 T5 T6 T T5 T4 T2 I T2 T6 T5 5 T T T3 I 0 T6 T2 T4 6 T 0 I T3 2 T I 0 T T4 T3 T 0

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Hence the H matrix of this code can be expressed as

H I3 I3 I3 I3 I3 I3 I3 H H H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5

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I3 I3 I3 I3 I3 I3 I3 I3 T3 T6 T2 T5 T T4 I3 0 T3 T4 T T6 T5 0 I3 T T5 T3 T2 T4

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The resultant H matrix in an echelon canonical form is equivalent to the matrix shown in Eq. (5.10). It is clear that this matrix satis es the properties shown in Eqs. (5.7), (5.8), and (5.9). The interesting properties of the Burton code, especially property 1 in Eq. (5.7), can make this an odd-weight-column SbEC code. Actually every column vector of the H matrix shown in Eq. (5.10) is of odd weight, and property 1 in Eq. (5.7) satis es De nition 3.4 of the odd-weight-column code (see Section 3.2).

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CODES FOR HIGH-SPEED MEMORIES II: BYTE ERROR CONTROL CODES

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Property 2 in Eq. 5:8 and property 3 in Eq. 5:9 express the sequential structure of this code. These properties are not particularly important when parallel decoding is employed, as required, for high-speed memories. Next we consider the double-byte error detection capability of these 2-redundant SbEC codes. Theorem 5.1 [FUJI77b] The double-byte error detection capability, Pd , of the 2-redundant k 2 b; kb SbEC code is given by Pd 1 k : 2b 1

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Proof The probability Pd is calculated by counting the fraction of double-byte errors that are detected by this code. Double-byte errors, say E1 and E2 , generate a syndrome that may equal the syndrome caused by a single-byte error, say E3. This will result in a miscorrection as stated before. We analyze the cases occurred by these byte errors of E1 , E2 , and E3 , in the following: Case 1. E1 , E2 , and E3 are all in the information-bit part. Case 2. E1 and E2 are in the information-bit part, and E3 in the check-bit part. Case 3. E1 is in the information-bit part, and E2 and E3 in the check-bit part. Case 4. E1 , E2 , and E3 are all in the check-bit part. (The miscorrection will be harmless if it occurs.) For each case the number of miscorrections can be counted as follows: Case 1: 3 2b 1 k 3 ; k

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; Case 2: 2 3 2b 1 2 k Case 3: 3 2b 1 ; 1 Case 4: 0: Therefore the detection ability, Pd is as follows: & ' k k k 3 2b 1 2 3 2 1 b Pd 1 : k 2 P b b 2 j i; j 1 i By simple algebra, the equation above reduces to 1 fk= 2b 1 g, which completes the proof. Q.E.D.

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SINGLE-BYTE ERROR CORRECTING (SbEC) CODES

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Example 5.4 The 2-redundant 80; 64 S8EC code has the following double-byte error detection probability Pd 1 8= 28 1 0:9686. That is, 96:86% of all double-byte errors are detected, and therefore it is very nearly an S8EC-D8ED code. Theorem 5.1 gives us an important result that for a large value of b (e.g., b 8 and 16 bits), the 2-redundant SbEC code is very nearly an SbEC-DbED code. Also this result is practical and suitable for high-speed memories because the information-bit length of these memories is rather short [ARLA84]. Thus the class of SbEC-DbED codes discussed later may not be all that necessary for the case where b is large. Here, we consider a generalized class of Burton codes that can be constructed by using a generator polynomial g x xb 1 p x , where the degree of p x is l. It is important that if l is equal to b, the codes de ned by the polynomial g x are equal to the Burton codes. If l is greater than b, the codes can also correct all single-byte errors [VARA83]. If p x is a primitive polynomial of degree l, then the code length N (bits) and the check-bit length R can be expressed as N b 2l 1 ; R l b: If l is less than b, the codes can correct single-bit errors and detect both double-bit errors and single b-bit burst errors [VARA83]. This will be shown in Section 6.1. 5.1.3 Odd-Weight-Column Codes Fujiwara Codes

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From the property of the Burton code Fujiwara derives a new class of SbEC codes that has an odd-weight-column characteristic [FUJI77b, FUJI78]. This generalized code over GF 2b includes an excellent odd-weight-column SEC-DED code, especially for b 1. In an odd-weight-column matrix code over GF 2b (see De nition 3.4 in Section 3.2), no two columns are identical and no column is all zero or a multiple of another column. The last is true because if a column vector hi is a multiple of hj (i.e., hi b hj , where b 2 GF 2b , and b 6 0; b 6 1), then sum of the elements of hi equals b, contradicting the odd-weight-column property. Therefore the columns hi and hj are a linearly independent pair and the code is of distance-3 or higher. And we have proved the following. Theorem 5.2 An odd-weight-column matrix code over GF 2b is an SbEC code.

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Lemma 5.1 There exists exactly 2b r 1 odd-weight-column vectors, each having r elements over GF 2b . Proof Let hi be the i-th odd-weight-column vector over GF 2b in the parity-check matrix of this code. Also let the sum of arbitrary r 1 elements in hi be g 2 GF 2b . Then the remaining one element can be determined as g I, where I is an identity element in GF 2b ; that is, the remaining one element in hi is uniquely determined from the other r 1 elements. Since each element can have any one of 2b values, there are exactly 2b r 1 such column vectors. Q.E.D.

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