Codes for High-Speed Memories II: Byte Error Control Codes in .NET

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Codes for High-Speed Memories II: Byte Error Control Codes
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In the application of error correcting codes to computer systems, there are a number of situations where an error-correcting code capable of correcting clusters of adjacent bits in error is uniquely suited. An example is errors due to a failure in a b-bit organized semiconductor memory chip, which is called a byte-organized memory chip. In this chapter we refer to this cluster of b bits, b ! 2, as a byte. With the advent of high-density semiconductor memory chips, these b-bit organized RAM chips, for example, b 4; 8; 16, and 32 bits organized RAM chips, have been fabricated and are now marketed. If a failure occurs in such a chip, the resulting information read out from the memory is likely to have the b-bit cluster in error. In this kind of application it may be desirable to have an error control code capable of correcting / detecting byte errors as well as bit errors [FUJI82, HORI83, CHEN83, DENG87, FUJI90]. The recent high-density RAM chip with wide input / output (I / O) data of 8, 16, and 32 bits has an inside structure organized by multiple subarrays almost physically separated from each other. For this organization more suitable byte error control codes have been studied. This chapter deals with design of practical byte error correcting / detecting codes for high-speed semiconductor memories. From a practical standpoint, it is about the code design method for controlling at most double-byte errors. These practical code classes are abbreviated and designated as follows: 1. SbEC codes: Single b-bit byte error correcting codes. 2. SbEC-DbED codes: Single b-bit byte error correcting and double b-bit byte error detecting codes.
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Code Design for Dependable Systems: Theory and Practical Applications, by Eiji Fujiwara Copyright # 2006 John Wiley & Sons, Inc.
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3. SbEC-Sp b=B ED codes: Single b-bit byte error correcting and single p-byte within a B-bit block error detecting codes. The SbEC-DbED codes have found many applications in recent large capacity semiconductor memory systems with b 4 bits byte size. The SbEC-Sp b=B ED codes with b 4; p 2, and B 16 have also been applied to large-capacity high-speed memory systems using RAM chips each having 16-bit I / O data.
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In this section we discuss a class of single-symbol error correcting codes over GF 2b . Each symbol is a b-bit byte, and therefore the codes are called SbEC codes. 5.1.1 Hamming-Type Codes
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It is well known that a Hamming single-error correcting code can be constructed by elements from any nite eld [HAMM50]. If F is such a eld, then the H matrix for the single-error correcting code with elements from F is constructed as follows: Choose as columns of the H matrix all the nonzero r-tuples of elements from F such that no column of H is a multiple of another column. Then, since every pair of columns is linearly independent, the code has dmin 3, that is, the code is capable of correcting single (symbol) errors. If, in particular, F is GF 2b , these Hamming codes are an SbEC class of codes. To implement the Hamming-type SbEC code, it is necessary to transform the H matrix over GF 2b to a binary form as follows [BOSS70, HONG72]. De nition 5.1 Given a binary primitive polynomial g x of degree b, the companion matrix T corresponding to g x is de ned as
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Let a be a primitive element in GF 2b and a root of g x . Its companion matrix T j j has as its columns ai for i 1; 2; . . . ; b, where ai is the coef cient vector of j j i x mod g x .
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