Figure 4.14 On-chip ECC for the ROM chip. in .NET

Creator qr-codes in .NET Figure 4.14 On-chip ECC for the ROM chip.
Figure 4.14 On-chip ECC for the ROM chip.
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: Memory unit that stores information bit : Memory unit that stores check bit
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from the ROM and entered to the ECC circuit. The corrected 32 information bits are transferred to a nibble decoder and divided into four blocks. The output buffer drives 8 bits. According to [SHIN83], the ECC circuit consumes less than 20% of the total chip area. Even though it increases the chip area, the theoretical yield can be enhanced by a factor of 3 at about 2.5 particles/cm2 defect density. The access time increase by the ECC circuit is less than 15%. As another practical example, semi-distance codes, a class of asymmetric error masking codes [BLAU93], have been applied to ROM bus line circuits [MATS88, 90]. The faults caused by open- or short-circuit defects in the bus lines can be made asymmetric by controlling the bus drivers and the bus terminal gates. These asymmetric faults are tolerated by using new codes based on the concept of semi-distance [MATS90]. The technique has the unique feature that no error correction circuits are required, and therefore additional circuits are very small. 4.3.3 Further Discussion on Recent Memory On-Chip ECCs
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Application of the Hamming 136; 128 SEC codes to 16 M-bit DRAM chips may be an option for tolerating soft error problems. It can relax the problems of circuit area overhead and error correction operating time. The on-chip ECC circuit requires 12% to 20% chip overhead and around 10% access time penalty [FURU89, ARIM90]. For the experimental 1 M-bit cache DRAM [ASAK90], which consists of 1 M-bit DRAM operating as a main memory and 8 K-bit SRAM as a cache, 40; 32 modi ed Hamming SEC-DED code has been applied to the DRAM part in the chip. On-chip ECC circuit requires 12 ns access penalty, amounting to a 15% access time overhead and around a 15% chip area overhead. The soft-error rate is improved by more than ten orders of magnitude. Augmented Product Code (APC) A new class of product codes, called an augmented product code (APC) with double-bit error correction capability, has been applied to the DRAM chip whose memory cell capacitors have a trench structure [MAZU92]. It is known that if the a-particles are incident to the intervening space between two-adjoining vertically mounted trench capacitors, the resulting plasma discharge may delete the data in both capacitors. This is a simulation result of the charge-sharing mechanism due to a-particle-induced plasma shorts between adjoining capacitors [CHER86]. The trench capacitors produce double-bit upsets very frequently in a DRAM chip. For example, take a rectangular subarray of size m1 m2 , that is, a subarray of m2 memory cells in each of its m1 word-lines. To construct a product code, or a cross-parity code, for each word line, we organize the m2 cells in the form of a logical rectangular array of size p 1 q 1 where m information bits describe the inner array p q m, and the p 1 -th (bottom-most) row and the q 1 -th (right-most) column consist of parity bits. In this case, if m1 m2 m2 , the DRAM is called a nonredundant one, but a fault-tolerant DRAM requires m1 m2 > m2 . The augmented product code (APC) is constructed by adding a set of p-diagonal parity bits (if p ! q) to the regular horizontal and vertical parity bits (p q 1 bits) of the product code. That is, the code requires 2p q 1 check bits. This pq; pq 2p q 1 APC is a distance-5 code, so it can correct all double-bit errors in the readout word, including these parity bits. The on-chip APC is evaluated for 1 M-bit to 64 M-bit DRAMs such that chip area overhead is around 10% to 15% and timing overhead is 14% to 18%.
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