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Rotational codes offer modularity of the encoding / decoding circuits with small additional check bits, and hence they are practical for LSI / VLSI implementation of the encoder / decoder [FUJI80]. 3.5.1 Code Concept
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De nition 3.8 A code whose H matrix has the following d submatrices, each having r rows and n=d columns is called a rotational code. In this case, d is a divisor of r and of n. H H0 jH1 j . . . jHj j . . . jHd 1 r n ; Hj R H0 ;
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j 1; 2; . . . ; d 1;
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In this de nition H0 and R are called the generating submatrix and the rotational operating matrix, respectively. The H matrix design of the rotational codes presents d cyclic shifts of the r=d rows in a vertical direction between adjacent submatrices. The unique feature of the rotational code is that its encoding / decoding circuit can be implemented with d identical subcircuits speci ed by the generating submatrix H0 , each by simply altering the input / output connections [CART73, BOSS74, FUJI77]. Therefore the rotational code gives a modularized encoding / decoding circuit suitable for LSI implementation [FUJI80]. In order to understand the concept of rotational code, a simple example is presented next. Example 3.6 The code expressed by the following H matrix can be made rotational by permuting its column vectors as shown below. In this case d r 4. Figure 3.1 shows the modularized decoding circuit based on H0 .
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Figure 3.1 Modularized decoding circuit for the rotational code H 0 .
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d0 1 1 1 0
d1 1 1 0 1
d2 1 0 1 1
d3 0 1 1 1
c0 1 0 0 0
c1 0 1 0 0
c2 0 0 1 0
c3 0 0 0 1
d0 c0 1 1 1 0 1 0 0 0 H0
d3 c1 0 0 1 1 1 0 1 0 H1 0 1
d2 c2 1 0 0 0 1 1 1 0 H2
d1 c3 1 0 1 0 0 0 1 1 H3
, H0 =
1 1 1 0
1 0 0 0
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0 1 0 0
0 0 1 0
0 0 0 1
1 0 0 0
Figure 3.1 shows four identical subscircuits, each having seven inputs and four outputs including signals communicating with other subcircuits. Also shown are the four-input parity checker, an inverter, a four-input AND gate, and an exclusive-OR (XOR) gate to give the whole decoding circuit speci ed by the rotational (8, 4) SEC-DED code. Modularity is the main feature of this decoder. In 4 the original (8, 4) oddweight-column SEC-DED code will be described in Example 4.1. Its decoding circuit shown in Figure 4.1 is transformed here to the rotational code H0 and its modularized decoding circuit shown in Figure 3.1. The matrix H0 is identical to the original matrix H because the column vectors in H0 are just a permutation of those in H. 3.5.2 Maximum Code Length of Rotational Codes
A simple example of the rotational code is a rotational single-bit error correcting (SEC) code. Other rotational memory codes, such as the rotational single-byte error correcting (SbEC) codes, rotational single-byte error correcting and double-byte error detecting (SbEC-DbED) codes, will be demonstrated in later chapters. De nition 3.9 Let the i-th cyclic shift of a vector H h0 h1 . . . hr 1 be denoted by H i hi hi 1 . . . hr 1 h0 . . . hi 1 :
A set of all distinct vectors obtained by cyclic shifts of a vector is called a cyclic equivalence class. & Example 3.7 The cyclic equivalence classes of binary 4-tuples sequences are as follows: E1 f0000g; E2 f1111g; E3 f1010; 0101g; E4 f0001; 0010; 0100; 1000g; E5 f0011; 0110; 1100; 1001g; E6 f0111; 1110; 1101; 1011g: Each cyclic equivalence class (of r-tuples) will have m vectors, where m is a divisor of r. If m 6 r for any class, then it is called a degenerate cyclic equivalence class. In the example, E1 , E2 , and E3 are degenerate cyclic equivalence classes, whereas E4 , E5 , and E6 are nondegenerate cyclic equivalence classes. In general, for r and q-ary sequence the number of nondegenerate cyclic equivalence classes, Nq r , is given as follows [GOLO58]: Nq r 1X m m qr=m : r mjr 3:5
P Here mjr expresses summation over all m that divides r, and m m is Mobius function [PETE72] de ned as m m 1 1; 0; 1 l ; m 1; m has any square factor; m p1 p2 . . . pl ; where pi s are distinct primes:
Values of m m for m 1 to 15 are shown below: m 1 2 3 4 0 5 1 6 1 7 8 9 0 10 1 11 1 12 0 13 1 14 15 1 1