HSEC

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The corresponding codeword v d0 d1 d2 d3 c0 c1 c2 has four data bits in the former four positions in v and three check bits in the latter three positions. The check bits are computed by the following equations over GF 2 : c0 d0 d1 d2 ; c1 d0 d2 d3 ; c2 d0 d1 d3 : At the start of decoding the following syndrome calculation is performed for the 0 0 0 0 received word r d0 d1 d2 d3 c00 c01 c02 :

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0 0 0 S0 d0 d1 d2 c00 ; 0 0 0 S1 d0 d2 d3 c01 ; 0 0 0 S2 d0 d1 d3 c02 :

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The syndrome obtained from the calculation above is denoted as S S0 S1 S2 , which indicates the erroneous bit positions if single-bit errors occur. That is, if the binary syndrome pattern is identical to a particular binary column vector in H, then the bit corresponding to the column vector is determined to be in error. The indicated bit is inverted and nally corrected. Suppose that in the example code above the second bit d1 is in error. We then obtain the syndrome S 1 0 1 , which is identical to the second column vector in H. Therefore the second bit in r is inverted and nally corrected. b b b b Figure 2.5 shows the encoder and the decoder of this code, where d0 , d1 , d2 , and d3 are the decoded output data. If double-bit errors occur, there is the risk of miscorrection. In the 7; 4 code of this example, if the d2 and d3 bits are in error, then S 110 011 101 , which indicates that the d1 bit is in error. So the d1 bit will be corrected, that is, miscorrected. In this example code, if the second column is deleted from the HSEC , which then expresses a 6; 3 SEC code, the double-bit errors given above will lead to no miscorrection. In general, if the nonzero syndrome pattern is not identical to any column vectors in HSEC , then the errors can be detected. From the example above we can easily design the binary SEC code. The H matrix of the binary SEC code is constructed by choosing distinct nonzero binary column vectors.

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BASIC MATRIX CODES

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d0 d1 d2 d3

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Input data

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d0 d1 d2 d3 c0 c1 c2

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Encoded output data

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: 3-Input parity checker (3-Input modulo-2 adder)

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(a) Encoder

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d0 d1 d2 d3

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Decoded output data

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c0 c1 c2

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Received data

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S0 S1 S2

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: 4-Input parity checker (4-Input modulo-2 adder) : Exclusive-OR gate : 3-Input AND gate : Inverter gate

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(b) Decoder

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Figure 2.5 Encoder and decoder of the Hamming (7, 4) SEC code.

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The maximum number of these columns is 2r 1. In other words, the maximum code length of a binary n; k SEC code is n 2n k 1, where n k r. The code whose code length is less than the maximum length is called a shortened code. The shortened code has a possibility to detect some additional errors beyond the guaranteed error control capability of the code.

MATHEMATICAL BACKGROUND AND MATRIX CODES

The n; k binary SEC codes, in general, have the following code parameters: Check-bit length r n k. Maximum code length in bits n 2r 1. Maximum information-bit length (or data length in bits) k n r 2r 1 r. 2.3.3 Hamming Single Error Correcting and Double Error Detecting (SEC-DED) Codes The distance-4 code is a single error correcting and double error detecting code that is called a Hamming SEC-DED code [HAMM50]. The code is designed by adding a simple parity check of n bits to the SEC codes. That is, the H matrix of this code is designed by adding a row vector with all 1 s, and also adding a weight-1 column vector with upper r 1 all 0 s to the r 1 n 1 H matrix of the binary SEC code. The H matrix, denoted as HSEC DED , is written as