FIXED-BYTE ERROR CONTROL UEC CODES in .NET

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FIXED-BYTE ERROR CONTROL UEC CODES
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I b I r : O: P: Q: Me:
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b b r r identity matrix, zero matrix, r b b matrix having distinct b nonzero even-weight columns, matrix whose columns are repetitions of the rst column in I b , matrix having r b -bit nonzero even-weight columns except for b 1 columns obtained by adding the rst column in P to each remaining column in P as well as for the rst column in P, M o : matrix having r b -bit odd-weight columns except for weight-one columns.
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Proof Since nonzero column vectors in H are all distinct and odd weight, the code satis es conditions 1, 2, and 6 of Theorem 10.4 for the error set E1 ; therefore the code has the SEC-DED function. Since the matrix Ib is nonsingular, the code satis es conditions 1 and 3 in the xed-byte X0 for the error set E0 . It is easy to see that the syndrome caused by any byte error in X0 is not equal to the syndrome caused by any single-bit error in X1 . So condition 4 holds. Figure 10.7 shows the syndrome patterns caused by byte errors in X0 and by double-bit errors in X1 . Note that the syndromes caused by byte errors are distinct from those caused by double-bit errors, so condition 5 holds. Based on the above, the H matrix given in this theorem satis es all the conditions of Theorem 10.4 and therefore is the parity-check matrix of the FbECjSEC-DED code. Since the matrices Me and Mo have the maximum number of columns, 2r b 1 b 1 and 2r b 1 r b , respectively, the maximum length (in bits) of this code can be expressed as Nmax b 2r b 1 b 1 2r b 1 r b r 2r b b 1:
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(a) Syndrome patterns of byte errors in X0 0 1 One 1 1 One 1 One column in Me
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Figure 10.7 Syndrome patterns caused by byte errors in X0 and also by double-bit errors occurring outside X0 . Source: [FUJI98]. 1998 IEEE.
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CODES FOR UNEQUAL ERROR CONTROL / PROTECTION (UEC / UEP)
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This is equal to the maximum code length (in bits) of the FbECjSEC-DED code given in Theorem 10.5. Q.E.D. Consequently the code indicated in Theorem 10.8 is optimal. Example 10.2 (19, 11) F4ECjSEC-DED Code 1000 6 0100 6 6 0010 6 6 0001 H 6 6 0110 6 6 1101 6 4 0011 1000 2 111 000 000 000 101 011 110 000 0000 0000 0000 0000 1110 1101 1011 0111 3 10000000 01000000 7 7 00100000 7 7 00010000 7 7: 00001000 7 7 00000100 7 7 00000010 5 00000001
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Evaluation The FbECjSEC-DED codes are evaluated from the perspectives of error detection capabilities and decoder hardware amount. The FbECjSEC-DED codes sometimes miscorrect b-bit burst errors and random triplebit errors, some of which are beyond the original error correction / detection capabilities of the code, as single-bit errors in X1 or as xed-byte errors in X0 . Table 10.5 shows the miscorrection tendencies of the example codes with information-bit lengths k 32, 64, and 128, which are shortened k r; k FbECjSEC-DED codes with k 32, 64, and 128 bits. Here the reader should recall Theorems 10.6 and 10.7 that the byte plus single-bit or double-bit errors do not miscorrect any bits in the xed-byte X0 in the FbECjSEC-DED code. The table indicates that the miscorrection of xed-byte X0 is very small, and therefore the xed-byte X0 has strong error protection against multiple-bit errors. The FbECjSEC-DED code does not require large decoding hardware augmentation compared to the existing SEC-DED code. For example, the decoder of the (75, 64) F4ECjSEC-DED code requires 15.49% larger hardware than the (72, 64)SEC-DED code.
TABLE 10.5 Miscorrection Rates of (k +r ; k ) FbECjSEC-DED Codes b-Bit burst errors b k r Miscorrect single bit in X1 (%) 4 8 12 4 8 12 4 8 12 32 32 32 64 64 64 128 128 128 10 14 18 11 15 19 12 16 20 17.55 17.13 10.38 16.81 21.97 18.60 24.21 31.27 28.94 Miscorrect fixed-byte X0 (%) 0.63 1.23 1.33 0.51 0.89 0.81 0.09 0.41 0.41 Triple-bit errors Miscorrect single bit in X1 (%) 35.11 19.06 12.50 43.02 29.93 20.57 52.39 43.58 36.20 Miscorrect fixed-byte X0 (%) 1.17 0.91 0.75 0.63 0.56 0.50 0.29 0.27 0.27