PARALLEL DECODING BURST / BYTE ERROR CONTROL CODES in .NET

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PARALLEL DECODING BURST / BYTE ERROR CONTROL CODES
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(e) Suppose that the syndrome generated by a received word is S 011011111 T . Show that frame 2 is corrupted by an error pattern 001110000 . (f) Suppose that the syndrome generated by a received word is S 011111010 T . Show that none of the frames (from frame 0 to frame 5) results in a correctable 3-bit burst error pattern. 8.6 The 2-input XOR function is expressed as F A B A B A B with OR, NAND, and AND gates. Explain how a glitch may be generated when the inputs (A, B) change from (0, 1) to (1, 0). Construct an 8-input XOR circuit using seven 2-input XOR gates in a perfect binary tree, and obtain the TAG frequency table for all transient weight of the circuit. Use the transient behavior of the XOR functions shown in Table 8.2 to determine the worst-case TAG number of this 8-input XOR circuit when all inputs receive transient T s. For the syndrome generation circuit of Hsiao s (13, 8) SEC-DED code shown in Eq. (8.6), answer the following questions:
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0 0 0 0 0 0 (a) For the received 9 inputs of d0 N ; d1 N ; d2 N ; d3 T ; d4 N , d5 N , 0 0 0 d6 N , d7 N , and c0 T (i.e., WT 2), indicate the T and G marks at the inputs and the outputs of each XOR gate in the syndrome S0 generation circuit. (b) In the above S0 circuit, count the temporal accumulated glitches (TAGs). (c) There are 9 36 transient patterns of WT 2. Count among them the 2 frequency for TAG 4. (d) Using Eqs. (8.12) and (8.13), nd the maximum TAGs of this S0 circuit. (e) Design the gate-shared syndrome generation circuit of the code, and discuss the difference of TAG probabilities of the gate-shared circuit and the nonshared circuit.
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[BAI01] G. Bai, S. Bobba, and I. N. Hajj, Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits, Proc. Design Automation Conf. (June 2001): 295 300. [BENI00] L. Benini, G. D. Micheli, A. Macii, M. Poncino, and R. Scarsi, Glitch Power Minimization by Selective Gate Freezing, IEEE Trans. VLSI Syst., 8 (June 2000): 287 298. [CHEN97] H. H. Chen and D. D. Ling, Power Supply Noise Analysis Methodology for Deepsubmicron VLSI Chip Design, Proc. IEEE Design Automation Conf. (June 1997): 638 643. [CHIE69] R. T. Chien, Burst-Correcting Codes with High-Speed Decoding, IEEE Trans. Info. Theory, IT-15 (January 1969): 109 113. [ELSP62] B. Elspas and R. A. Short, A Note on Optimum Burst-Error-Correcting Codes, IRE Trans. Info. Theory, IT-9 (January 1962): 39 42. [FUJI02] E. Fujiwara, K. Namba, and M. Kitakami, Parallel Decoding for Burst Error Control Codes (in Japanese), Trans. IEICE Japan, J85-A (November 2002): 1284 1295. (Translated into English in: Electron. Commun. in Japan, 87 (January 2004): 38 48). [GHOS04] S. Ghosh, S. Basu, and N. A. Touba, Reducing Power Consumption in Memory ECC Checkers, Proc. IEEE Int. Test Conf. (October 2004).
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[HAMA97] M. Hamada and E. Fujiwara, A Class of Error Control Codes for Byte Organized Memory Systems SbEC- Sb S ED Codes , IEEE Trans. Comput., 46 (January 1997): 105 109. [HONG72] S. J. Hong and A. M. Patel, A General Class of Maximal Codes for Computer Applications, IEEE Trans. Comput., C-21 (December 1972): 1322 1331. [JIAN00] Y.-M. Jiang, A. Krstic, and K.-T. Cheng, Dynamic Timing Analysis Considering Power Supply Noise Effects, Proc. Int. Symp. on Quality of Electronic Design (March 2000): 137 144. [KASA62a] T. Kasami, Systematic Cyclic Codes for Burst Error Correction (in Japanese), J. IEICE, 45 (January 1962): 9 16. [KASA62b] T. Kasami, Burst Error Correcting Codes Constructed by Computer (in Japanese), J. IECE Japan, 45 (November 1962): 1527 1532. [LAVA93] L. Lavagno and A. Sangiovanni-Vincentelli, Algorithms for Synthesis and Testing of Asynchronous Circuits, Kluwer Academic (1993). [LO05] J. C. Lo, Y. L. Wan, and E. Fujiwara, Transient Behavior of the Encoding / Decoding Circuits of Error Control Codes, Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (October 2005): 120 128. [MEGG61] J. E. Meggitt, Error Correcting Codes and Their Implementation for Data Transmission Systems, IRE Trans. Info. Theory, IT-7 (1961): 232 244. [MEHT95] H. Mehta, M. Borah, R. M. Owens, and M. J. Irwin, Accurate Estimation of Combinational Circuit Activity, Proc. IEEE Design Automation Conf. (June 1995): 618 622. [NISH97] H. Nishihara and S. Ura, Introduction to Optical Electronics (in Japanese), Corona Publishing (1997). [PARR01] P. Parra, A. J. Acosta, and M. Valencia, Reduction of Switching Noise in Digital CMOS Circuits by Pin Swapping of Library Cells, Proc. Int. Workshop Power and Timing Modeling, Optimization and Simulation (September 2001): paper 9.3. [PETE72] W. W. Peterson and E. J. Weldon Jr., Error-Correcting Codes, 2d ed., MIT Press (1972). [ROSS04] D. Rossi, A Muccio, A. K. Nieuwland, A. Katoch, and C. Metra, Impact of ECCs on Simultaneous Switching Output Noise for On-Chip Buses of High Reliability Systems, Proc. IEEE Int. Online Test Symp. (July 2004): 135 140. [ROY99] Y. Y. ans K. Roy and R. Drechsler, Power Consumption in XOR-Based Circuits, Proc. Asian and South Paci c Design Automation Conf. (January 1999): 299 302. [TANG02] K. T. Tang and E. G. Friedman, Simultaneous Switching Noise in On-Chip CMOS Power Distribution Networks, IEEE Trans. VLSI Syst., 10, 4 (August 2002): 487 493. [UMAN03] G. Umanesan and E. Fujiwara, Parallel Decoding Burst Error Correcting Codes, Proc. IEEE Int. Symp. on Information Theory, (July 2003): 420. [UMAN05] G. Umanesan and E. Fujiwara, Parallel Decoding Cyclic Burst Error Correcting Codes, IEEE Trans. Comput., 54 (January 2005): 87 92. [ZHOU00] H. Zhou and D. F. Wong, Optimal Low Power XOR Gate Decomposition, Proc. IEEE Design Automation Conf. (June 2000): 104 107.
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CONTENTS 9.1 Error Location of Faulty Packages and Faulty Chips . . . . . . . . . . . . . . . . . . 9.2 Block Error Locating (Sb=p b EL) Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Single-Bit Error Correcting and Single-Block Error Locating (SEC-Sb=p b EL) Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Code Conditions and Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.2 Design for SEC-Sb=p b EL Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. Codes Designed by Tensor Product Codes I . . . . . . . . . . . . . . . 2. Codes Designed by Odd / Even-Weight Column Square Matrices Codes II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.3 Decoding Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.4 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Single-Bit Error Correcting and Single-Byte Error Locating (SEC-Se=b EL) Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 Code Conditions and Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2 Design for SEC-Se=b EL Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Burst Error Locating Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Frame Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 Burst Error Locating (Bl EL) Codes . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.3 Single-Bit Error Correcting and Burst Error Locating (SEC-Bl EL) Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.4 Decoding Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.5 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 Code Conditions of Error Locating Codes . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.2 Code Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.3 Relation between Error Locating Codes and Error Correcting / Detecting Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 376 377 377 379 379 380 386 387 389 389 392 393 396 396 397 398 402 402 404 404 405 408 409 410
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