PARALLEL DECODING BURST / BYTE ERROR CONTROL CODES in .NET

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PARALLEL DECODING BURST / BYTE ERROR CONTROL CODES
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d7 (T) d6 (T) d5 (N) d4 (N) d3 (N) d2 (T) d1 (T) d0 (N) WT = 4 TAG = (1+1) + (1+1+1) + (1+2+1+1+1) = 11 T T T T N N N N
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Figure 8.22 Encoding circuit of the (13, 8) SEC-DED code with shared XOR gates. Source: [LO05]. 2005 IEEE.
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Another potential solution is to insert pipeline registers. Figure 8.24 shows an example of how pipeline registers ( ip- ops) are inserted in the c0 circuit of the (13, 8) SEC-DED encoding circuit. The 5-input XOR function is constructed in three stages. The ip- ops are inserted at each stage. In the schematic of Figure 8.24, note that d7 is connected directly to the XOR gate at the third stage. However, for the pipeline operations each stage holds the different intermediate results from different data inputs. Therefore two ip- ops are inserted in the d7 line such that it can hold different data and be synchronized with the rest of the circuit. Recall from the previous examples that the accumulation of glitches is mainly due to the easy propagation of glitches by an XOR gate. The pipeline register can effectively lter out the glitches and thus guarantee no glitch propagation. Note that while G can
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Figure 8.23 TAG probabilities plots of the (13, 8) SEC-DED encoding circuit and of the gate-shared version.
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Source: [LO05]. 2005 IEEE.
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Figure 8.24 Encoding circuit for c0 of the (13, 8) SEC-DED code with pipeline register (flip-flops) inserted.
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Source: [LO05]. 2005 IEEE.
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be blocked by the ip- op, T will not be ltered out. In this extreme example the worst-case scenario, with all ve inputs having T, will generate only two glitches, or TAG 2. Recall that the worst case is TAG 6 for an 5-input XOR function without pipeline. We believe that the pipelining of the encoding / decoding circuits is inevitable for the ever-increasing word length. The insertion of pipeline registers will add to the hardware overhead as well as extra delay time. The rise in delay time due to the ip- ops is not a major concern because the performance is measured in throughput rather than the actual latency time of encoding data. Nevertheless, the scenario shown in Figure 8.24 is simply too costly for practical applications. The hardware overhead can be reduced by inserting pipeline registers every few XOR levels. However, this has to also be related to the targeted data rate of the overall design. 8.3.5 Maximum Temporal Accumulated Glitches (TAGs) and Matrix Code Design In the worst-case estimation technique presented previously, the mean and standard deviation are calculated directly from the maximum TAG numbers. The maximum TAG number can be further estimated with just the knowledge of how the 1 s in the H matrix is distributed. In other words, only a few simple steps will be needed to estimate the transient behavior of any error control code de ned by an H matrix, regardless of the information length. First, let s revisit the topic discussed previously about obtaining the TAG number in an XOR circuit. The upper bound of the number of TAG of an m-input XOR function can be calculated as follows: TAGm TAGm WT m m log2 m ; 2 8:12
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when m is a power of two and TAG1 0. If m is not a power of two, then we rst nd its binary form such that m ml 1 2l 1 ml 2 2l 2 m1 21 m0 20 ;
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PARALLEL DECODING BURST / BYTE ERROR CONTROL CODES
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where l dlog2 me. We assume that the m-input XOR function will be composed systematically with smaller XOR functions whose input numbers are all power of two. The worst-case TAG can be computed as TAGm
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