PARALLEL DECODING BURST ERROR CONTROL CODES in .NET

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PARALLEL DECODING BURST ERROR CONTROL CODES
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1 : Error E is an -bit burst erro r. 0 : Otherwise
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Figure 8.6 An l-bit burst error detecting circuit (circuit M in Figure 8.5). Source: [FUJI02]. 2002 IEICE Japan.
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Algorithm 8.2 for Optimal H y i Step 1. t : 0. Step 2. If t L, end; else w : 1. Step 3. Let V be a set of binary row vectors of length R and weight w. Step 4. If V fg, then w : w 1 and go to step 3. Step 5. Choose an arbitrary vector x from V and V : V fxg. Step 6. If xhi;j 0 and xhi;t 1 for all j 6 t, replace the t-th row of Hy by x, set i t : t 1, and go to step 2. Step 7. Go to step 4.
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Figure 8.7 Error pattern calculator for adjacent two frames. Source: [FUJI02]. 2002 IEICE Japan.
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PARALLEL DECODING BURST / BYTE ERROR CONTROL CODES
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Since Algorithm 8:2 considers all the possible cases, the Hy obtained is optimal. i Next we present an algorithm to nd out optimal By . In this case i 3 2 ui;0 6 ui;1 7 7 6 7 6 y Bi 6 ui;2 7; 7 6 . . 5 4 . ui;R L 1 where ui; j 0 j < R L is a binary row vector.
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Algorithm 8.3 for Optimal B y i Step 1. Set t : 0, w : 1. Let V be a set of binary row vectors of length R and weight 1. Step 2. If t R L, end. Step 3. If V fg, then w : w 1. V is a set of binary row vectors of length R and weight w, which cannot be represented as a linear combinations of ui; 0 , , ui; t 1 , but V is a set of all binary row vectors of length R and weight w for t 0: Step 4. Let x be an arbitrary vector in V, and V : V fxg. Step 5. If x Hi 6 0, go to step 3. Step 6. #Exclude from V all the vectors that can be represented as a linear combination of x and ui;0 , , ui;t 1 . Set ui;t : x, t : t 1, and go to step 2. Since Algorithm 8:3 considers all the possible cases, the By obtained is optimal. i 8.1.4 Evaluation and Discussion
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Circuit Gate Amount and Check-Bit Length Figure 8:8 shows the check-bit length and the parallel decoding circuit complexity of the Fire codes correcting burst
Fire codes + Generalized method + + with optimum H i and Bi Fire codes + Generalized method R = 24 Interleaved Hamming code (p = 4)
2,000
Check-bit length R
R = 16
R = 20 R = 12
R = 11
l=4 200
0 32 64 Information-bit length K 128
Figure 8.8 Check-bit lengths and gate amounts of parallel decoding circuits for 4 -bit burst error correcting codes. Source: [FUJI02]. IEICE Japan.
Gate amount
1,000
PARALLEL DECODING BURST ERROR CONTROL CODES
50,000 20,000 Gate amount 10,000 5,000 2,000 1,000
Fire codes + Generalized method Interleaved Fire codes (p = 3 ) + Generalized method Interleaved Hamming codes (p = l = 12)
p : Interleaving degree
l = 12 500
1,024
Information-bit length K
Figure 8.9 Gate amounts of parallel decoding circuits for 12-bit burst error correcting codes. Source: [FUJI02].
2002 IEICE Japan.
errors of length l 4 bits. It also illustrates the hardware gate amount when Hy and By are i i optimal. Figures 8:9 and 8:10 illustrate the hardware complexity and the check-bit length of the Fire codes correcting burst errors of length l 12 bits. Figures 8:8, 8:9, and 8:10 also show the check-bit lengths and the hardware complexities of degree l interleaved single-bit error correcting Hamming codes, which are capable of correcting l-bit burst errors. In this case the decoding circuit consists of l number of decoding circuits for single-bit error correcting code placed in parallel. Here the 4-input AND, OR, and NOR gates are counted as 1 gate, and the 2-input exclusive-OR gates are counted as 1:5 gates. The hardware complexity of the proposed decoding method is worse than that of decoding interleaved codes. However, the interleaved single-bit error correcting Hamming codes require many more check bits than the Fire codes with same burst error correction capability. In general,
Fire codes Interleaved Fire codes (p = 3 ) Interleaved R = 84 Hamming codes (p = l = 12) R = 72 p : Interleaving R = 60 degree