Codes for High-Speed Memories IV: Spotty Byte Error Control Codes in .NET

Implement qr codes in .NET Codes for High-Speed Memories IV: Spotty Byte Error Control Codes
Codes for High-Speed Memories IV: Spotty Byte Error Control Codes
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Some of the error control codes mentioned in the previous chapters have been applied to high-speed memory systems using RAM chips with either 1-bit I/O data b 1 or 4-bit I/O data b 4 . However, modern large-capacity memory systems use RAM chips with 8, 16, or 32 bits of I/O data. A new class of codes called spotty byte error control codes has been developed for those memory systems that use high-density DRAM chips with wide I/O data [UMAN03a, 03b, KASH04, SUZU04, 05a, 05b]. Spotty byte error is a special type of byte error, de ned as a t-bit error in a b-bit byte, where 1 t b. This is based on the fact that the dominant errors in byte-organized chips, even in RAM chips with 8-bit, 16-bit, and 32-bit I/O data, are single-bit errors, or at most double-bit or triple-bit errors, which are sometimes called low-density byte errors [TANI92], or sparse byte errors. Spotty byte error control codes, called t=b-error control codes, where t is larger than or equal to 2 and less than at most b=2, are more practical than the conventional byte error control codes because they require smaller number of check bits than the existing byte error control codes. Here we deal with designing the code having spotty byte error length t as taking any value from 1 to b. It is apparent that if t 1, the codes are bit error control codes, and if t b, the codes are byte error control codes. In order to determine the code functions effectively applied to the solid-state data recorder of the satellite systems, the encoder and decoder of some spotty byte error control codes have been designed and implemented by FPGA to evaluate gate count and decoding delays [KANE05].
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Code Design for Dependable Systems: Theory and Practical Applications, by Eiji Fujiwara Copyright # 2006 John Wiley & Sons, Inc.
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Large-capacity high-speed memory systems often adopt high-density DRAM chips with wide I/O data. Examples of this type of recent DRAM architecture are 16 Mb chips with 8-bit I/O data [NUMA89], 256 Mb chips with 16-bit I/O data [SUGI93], 16 Mb chips with 16-bit I/O data [SUNA95], and 256 Mb chips with 32-bit I/O data [SAEK96, WATA96]. Because of their high-density nature, these DRAM chips are strongly vulnerable to aparticles, neutrons, and so forth. [ZIEG96, OGOR96, SRIN96, MASS96]. In particular, the large-capacity memory systems used at airplane altitudes or in a cosmic environment, that is, memories in aircraft and spacecraft, need to be protected from high-energy neutrons and cosmic rays. From the coding standpoint the multiple errors that occur within a chip can result in a byte error with only a few corrupted random bits. This is why we call such error a spotty error, meaning that only two or three bits (i.e., less than b=2 bits) are corrupted in a byte. We also refer to spotty errors within a byte as spotty byte errors. The burst / byte error detecting codes with the SEC capability do not correct any multiple random bit errors occurring within a single byte. Whereas the SbEC codes and SbEC-DbED codes can correct any single-byte errors, they require many check bits proportional to the byte size b. The byte error control codes treat a chip output as a byte. The minimum number of check bits required by the SbEC codes and SbEC-DbED codes is at least 2b bits and 3b bits, respectively. For example, an S16EC code applied to a memory system that adopts RAM chips with 16-bit I/O data requires 32 check bits. For practical information lengths of 64, 128, and 256 bits, 32-bit or larger redundancy, in general, is not preferable. Spotty byte error control codes, namely t=b-error control codes, offer a better practical solution to such problems. For mathematical tractability, spotty byte errors are denoted as t=b-errors, which stands for random t-bit errors occurring within a single b-bit byte. In this chapter we use a t=b-error to represent a binary row vector E 2 GF 2b such that 1 w E t, where w E is the Hamming weight of E, and we often take the value of t as being either 2 or 3 and the value of b as being 8 or 16 for the practical parameters of the spotty byte errors. In this chapter we deal with two types of spotty byte errors: s-spotty byte errors and mspotty byte errors. An s-spotty byte error is de ned as a set of random t or fewer bits errors con ned to a b-bit byte, and an m-spotty byte error is de ned as multiple spotty byte errors concentrated in one byte or distributed in multiple bytes. Sections 7.2 through 7.4 present a class of m-spotty byte error control codes correcting one spotty byte error, and codes detecting single-byte errors or two m-spotty byte errors besides correcting one spotty byte error. Section 7.5 shows a general class of s-spotty byte error control codes and m-spotty byte error control codes, both of which can correct and detect any number of spotty byte errors.
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