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Consider a code capable of adjacent double-bit error correction and single-byte error detection (ADEC-SbED) [UMAN02b]. (a) Find the necessary and suf cient conditions of such a code. (b) Prove that a linear binary (N, N R) ADEC-SbED code exists only if N (c) Prove that the null space of Iy O I Q2r 2 ! 2R 1 2b 1 b:
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is an ADEC-SbED code with code length in bits N b 2r and check-bit length R b r, where the elements in H are de ned as the following: O is an r b binary zero matrix, a, b are primitive elements of GF 2b and GF 2r r > 2 , respectively, I a0 a1 a2 ab 1 b b ; Iy ab 1 ab 2 ab 3 a0 b b , where ai denotes a binary column vector of GF 2b such that the i-th coordinate is one and all other coordinates are zeros for i 0; 1; 2; ; b 1, and Qi bi bi 1 bi 2 bi b 2 bi r b , where bi denotes a binary column vector of GF 2r for i 0; 1; 2; ; 2r 2. (d) Design the (128, 119) ADEC-S4ED code based on the H matrix presented in c . 6.22 Consider the codes capable of correcting adjacent double-bit errors occurring within a b-bit byte and detecting b-bit byte errors ((ADEC)b -SbED), where b > 2. (a) Find the necessary and suf cient conditions of such codes. (b) Prove that a linear binary (N, N R) (ADEC)b-SbED code exists only if " N b 2b 2R b 1 1 2b 1 !# :
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(c) Prove that the null space of H M0 M1 M2 Mn 1 ; T is an (ADEC)b-SbED code only if fai ; bi ; ai bi g faj ; bj ; aj bj g ;, where 0 i 6 j n 1, ; denotes the null set, Mi is an r b 2 b
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CODES FOR HIGH-SPEED MEMORIES III: BIT / BYTE ERROR CONTROL CODES
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for 0 i n 1, ai , bi 2 GF 2r f0g with r ! 4, ai 6 bi , and Ai is a binary b 2 b 2 nonsingular matrix [UMAN02c]. (d) Design the (72, 64) (ADEC)4-S4ED code and the (140, 128) (ADEC)8-S8ED code.
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REFERENCES
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[BOSS78] D. C. Bossen, L. C. Chang, and C. L. Chen, Measurement and Generation of Error Correcting Codes for Package Failures, IEEE Trans. Comput., C-27 (March 1978): 201 204. [BOYA87] I. M. Boyarinov, A. A. Davydov, and B. M. Shabanov, Error Correction in Main Memory of a High-Capacity Computer, Automation and Remote Control, Plenum (1987). (Original in Russian, Automatika i Telemekhanika, no. 7 [July 1987]: 152 165, 48 [July 1987]: 956 965.) [CHEN83] C. L. Chen, Error-Correcting Codes with Byte Error-Detection Capability, IEEE Trans. Comput., C-32 (July 1983): 615 621. [CHEN84] C. L. Chen and M. Y. Hsiao, Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review, IBM J. Res. Dev., 28 (March 1984): 124 134. [CHEN86] C. L. Chen, Error-Correcting Codes for Byte-Organized Memory Systems, IEEE Trans. Info. Theory, IT-32 (March 1986): 181 185. [CHEN92] C. L. Chen, Symbol Error-Correcting Codes for Computer Memory Systems, IEEE Trans. Comput., 41 (February 1992): 252 256. [CHEN98] C. L. Chen and M. Y. Hsiao, Error Detection and Correction for Four-Bit-per-Chip Memory System, US Patent 5,757,823 (May 26, 1998). [DAVY89] A. A. Davydov and A. Yu. Drozhzhina-Labinskaya, Length 4 byte error and double independent error correction by BCH code in semiconductor memories, Automation and Remote Control, 50 [November 1989]: 1570 1579, Plenum. (Original in Russian, Automatika i Telemekhanika, 50 [November 1989]: 135 145.) [DAVY91] A. A. Davydov and L. M. Tombak, An Alternative to the Hamming Code in the Class of SEC-DED Codes in Semiconductor Memory, IEEE Trans. Info. Theory, 37 (May 1991): 897 902. [DOET97] G. Doetting, K. J. Getziaff, B. Leppla, W. Lipponar, T. P ueger, T. Shlipf, D. Schmunkamp, and U. Wille, S/390 Parallel Enterprise Server Generation 3: A Balanced System and Cache Structure, IBM J. Res. Dev., 41 (July September 1997): 405 428. [DUNN83] L. A. Dunning and M. R. Varanasi, Code Constructions for Error Control in Byte Organized Memory Systems, IEEE Trans. Comput., C-32 (July 1983): 535 542. [DUNN85] L. A. Dunning, SEC-BED-DED Code for Error Control in Byte-Organized Memory Systems, IEEE Trans. Comput., C-34 (June 1985): 557 562.
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