SINGLE-BYTE ERROR CORRECTING AND DOUBLE-BIT ERROR CORRECTING (SbEC-DEC) CODES in .NET

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SINGLE-BYTE ERROR CORRECTING AND DOUBLE-BIT ERROR CORRECTING (SbEC-DEC) CODES
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Proof A codeword of length N (bits) can have N 2b 1 =b distinct single b-bit byte errors. The number of double-bit errors occurring within a B-bit block, not the single b-bit byte errors themselves, is N B b =2. From this we have 2R 1 2N K 1 N 1 ! 2b 1 N B b : b 2 By simple re-arrangement of variables in this inequality, we can show that the inequality in Theorem 6.30 holds. Q.E.D. Theorem 6.31 A binary linear SbEC-(DEC)B code needs at least 2b check bits.
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Proof An SbEC-(DEC)B code needs at least 2b check bits because conditions 2 and 3 of Theorem 6.29 imply that maximum 2b binary columns of the parity-check matrix H are linearly independent. Q.E.D. Code Design Method The code design method presented here uses short B; B R0 SbEC-DEC codes, shown previously in Subsection 6.3.1, to obtain practical SbEC(DEC)B codes with longer code lengths. The codes obtained by this method are practical in that they do not require too many redundant bits at the usual information-bit lengths and they are easily parallel decodable. Theorem 6.32 Let H be a parity-check matrix of a B; B R0 SbEC-DEC code. Let a be a primitive element of GF 2r such that r ! max b; dlog2 B 1 e . De ne the r B binary submatrix 2 6 M j 6 aj 4 j j aj 1 j aj 2 7 aj B 1 7 5 j 3
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j j j j j for 0 j 2r 2, where ak denotes the binary column vector of GF 2r for 0 2r 2. The null space of j " H H O H M0 H M1 H M 2r 2 #
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is an SbEC-(DEC)B code with code length in bits N 2r B and check-bit length R R0 r. Here O is an all zero r B binary submatrix. Proof Since H is a parity-check matrix of a B; B R0 SbEC-DEC code, we have T 6 T T E H 0, and also E1 H 6 E2 H for any E; E1 ; E2 2 fEb [ E2=B g with E1 E2 . 6 Therefore conditions 1 and 2 of Theorem 6.29 are clearly satis ed.
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CODES FOR HIGH-SPEED MEMORIES III: BIT / BYTE ERROR CONTROL CODES
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On the other hand, we observe that the condition r ! max b; dlog2 B 1 e implies that 2r ! B 1 and r ! b. Subsequently 2r ! B 1 implies that 0 6 E MT 2 GF 2r 0 for all E 2 E2=B , and r ! b implies that 0 6 E MT 2 GF 2r for all E 2 Eb . Therefore 0 for all E 2 fEb [ E2=B g, 0 6 E MT 2 GF 2r holds. Let E1 and E2 2 fEb [ E2=B g be 0 such that #T " #T H H E2 E1 Mj Mi " #T " #T H H E1 E2 Mi O "
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T T for 0 i 6 j < n. We know that E1 H E2 H implies E1 E2 because H itself is a T 0 parity-check matrix of a B; R SbEC-DEC code. Therefore E1 Mi E2 MT or j E1 MT E2 OT implies ai E1 MT aj E2 MT or ai E1 MT 0, where i 0 0 0 0 6 E1 MT E2 MT 2 GF 2r . This is a contradiction because 0 6 ai 6 aj ; thus 0 0 condition 3 of Theorem 6.29 is also satis ed. Q.E.D. As an example of the code we consider the practical case where the chip data output is 16 bits and the subarray data output is 4 bits, meaning b 4 and B 16. We need to choose r such that r ! b 4 and 2r ! B 1 17. This explains r ! 5. By using the (16, 7) S4EC-DEC code presented in [DAVY89] and taking r 5, we can design a S4EC-(DEC)16 code with code length N 25 16 512 bits and a check-bit length R 16 7 5 14. We can shorten this (512, 498) S4EC-(DEC)16 code to obtain a practical code with information-bit lengths 64, 128, and 256. Figure 6.25 shows the rst and the last four blocks of the (512, 498) S4EC-(DEC)16 code in binary form. Decoding Procedure Let v be the received word. The syndrome S can be calculated 0 as follows: v HT S S0 S1 , where S0 2 GF 2R and S1 2 GF 2r . Then H O H M0 H M1 ! ! H M2r 2 ! S0 : S1
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The syndrome vector S0 corresponds to the B; B R0 SbEC-DEC code. We can decode S0 by using any B; B R0 SbEC-DEC decoding methods [DAVY89, MASS96]. The decoding of S0 could detect an uncorrectable error pattern or yield a correctable error pattern E 2 fEb [ E2=B g. In the latter case, if S1 0, the rst block is in error; otherwise, we calculate E MT for 0 i 2r 2 until we nd some j, where 0 j 2r 2, such i that E MT S1 holds. If such a j is found successfully, the j 1 -th block is in error, j otherwise the error pattern is uncorrectable. Evaluation Figure 6.26 shows the relationship between the information-bit lengths and the check-bit lengths of the SbEC-(DEC)B codes designed by Theorem 6.32 and the SbEC(DEC)B bounds indicated in Theorem 6.30 for the two practical cases where B 16 and b 4, and B 8 and b 4. The S4EC-(DEC)8 code presented here requires only 12 check bits for the practical information length of 64 bits. Further, for longer information-bit lengths
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