CODES FOR HIGH-SPEED MEMORIES III: BIT / BYTE ERROR CONTROL CODES in .NET

Insert QR Code in .NET CODES FOR HIGH-SPEED MEMORIES III: BIT / BYTE ERROR CONTROL CODES
CODES FOR HIGH-SPEED MEMORIES III: BIT / BYTE ERROR CONTROL CODES
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are included in an additive coset of GF 2A except GF 2A itself, and 0 and I are the zero element and the identity element in GF 2b , respectively: 2 6 6 6 6 6 6 6 H 6Hr 6 6 6 6 6 4 0 . . . 0 0 . . . 0 0 . . . 0 3 " 7 7 7 t 7 7 7 # 7 7 7 " 7 7 7 r t 7 5 #
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3 I I I I 0 0 0 0 7 6 0 0 0 7 6 T i1 T j1 0 6 . . 7 . . . . . . . . . . . 6 . . 7 . . . . . . . . . . . 6 . . 7 . . . . . . . . . . . 7 6 6 T it 1 T jt 1 0 0 0 0 7 7 6 6 7 6 T it T jt I I I I 7 7 6 6 T it 1 T jt 1 T kt 1 7 7 6 6 . . 7 . . . . . . . . . . . 6 . . 7 . . . . . . . . . . . . 5 . . . . . . . . . . . 4 . ir 1 jr 1 kr 1 T T T X ! Y ! 2 i j k
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Proof Because every pair of columns in H is linearly independent, the H matrix satis es the SbEC function. Next we consider the case of three types of errors ocurring in the word. Let the two single-bit errors be E1 and E2 , and the single-byte error be E3 . Then there are ve cases of errors depending on the locations of the errors. 1. All errors are located in one part of the word, corresponding to the region including Hr in H, that is, region X indicated in H, or the region including Hr t in H, that is, the region Y in the H matrix not located in the span over the two regions. 2. Errors E1 (or E2 ) and E3 are located in the different bytes of region X, and an error E2 (or E1 ) is located in region Y. 3. Error E1 (or E2 ) is located in region X, and errors E2 (or E1 ) and E3 are located in the different bytes of region Y. 4. Error E3 is located in region X, and errors E1 and E2 are located in the different bytes of region Y. 5. Errors E1 and E2 are located in the different bytes of region X, and error E3 is located in region Y.
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In case 1, it is apparent that the indicated H matrix satis es the SbEC-DED function of Theorem 6.17 and the matrix shown in Eq. (6.9). In cases 2 and 3, the errors E1 and E2 cannot be miscorrected to error E3 depending on the structure of the matrix H. In case 4, the error E3 cannot be miscorrected to errors E1 and E2 for the nonzero error patterns of E1 , E2 , and E3 . As for case 5, let errors E1 and E2 be located in the i-th byte and the j-th byte of the region X, respectively, and also let error E3 be located in the k-th byte of region Y. Suppose that the errors E1 and E2 are miscorrected to error E3. Then the following relations hold: E1 E2 0; E 1 T E2 T E3 ;
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