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couldn t directly update the EFLAGS register (nowadays this is easy, because the two units are implemented on a single chip). This meant that the result of a floating-point comparison was written into a separate floating-point status register, which then had to be loaded into one of the general-purpose registers, and from there it was possible to test its value and perform a conditional branch. Let s look at an example.
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00401000 00401004 00401008 0040100A 0040100D FLD DWORD PTR [ESP+4] FCOMP DWORD PTR [ESP+8] FSTSW AX TEST AH,41 JNZ SHORT 0040101D
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This snippet loads one floating-point value into the floating-point stack (essentially like a floating-point register), and compares another value against the first value. Because the older FCOMP instruction is used, the result is stored in the floating-point status word. If the code were to use the newer FCOMIP instruction, the outcome would be written directly into EFLAGS, but this is a newer instruction that didn t exist in older versions of the processor. Because the result is stored in the floating-point status word, you need to somehow get it out of there in order to test the result of the comparison and perform a conditional branch. This is done using the FSTSW instruction, which copies the floating-point status word into the AX register. Once that value is in AX, you can test the specific flags and perform the conditional branch. The bottom line of all of this is that to translate this sequence into the decompiler s intermediate representation (which is not supposed to contain any architecture-specific details), the front end must understand this sequence for what it is, and eliminate the code that tests for specific flags (the constant 0x41) and so on. This is usually implemented by adding specific code in the front end that knows how to decipher these types of sequences.
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The code generated by a decompiler s front end is represented in a graph structure, where each code block is called a basic block (BB). This graph structure simply represents the control flow instructions present in the low-level machine code. Each BB ends with a control flow instruction such as a branch instruction, a call, or a ret, or with a label that is referenced by some branch instruction elsewhere in the code (because labels represent a control flow join). Blocks are defined for each code segment that is referenced elsewhere in the code, typically by a branch instruction. Additionally, a BB is created after every conditional branch instruction, so that a conditional branch instruction
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can either flow into the BB representing the branch target address or into the BB that contains the code immediately following the condition. This concept is illustrated in Figure 13.3. Note that to improve readability the actual code in Figure 13.3 is shown as IA-32 assembly language code, whereas in most decompilers BBs are represented using the decompiler s internal instruction set.
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EAX 1008 cryptex.00405050 ESI [<&KERNEL32.ReadFile>]
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TEST EAX,EAX JE SHORT cryptex.004010CB
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MOV EAX,[ESP+18] TEST EAX,EAX MOV DWORD PTR [ESP+14],1008 JE SHORT cryptex.004010C2
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LEA ECX,[ESP+14] PUSH ECX PUSH cryptex.00405050 PUSH 0 PUSH 1 PUSH 0 PUSH EAX CALL [<&ADVAPI32.CryptDecrypt>]
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TEST EAX,EAX JNZ SHORT cryptex.004010C2
004010A5 004010C2 004010C3 004010C8 004010C9 004010CA POP EDI MOV EAX,cryptex.00405050 POP ESI POP ECX RETN
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PUSH EDI PUSH cryptex.004030E8 CALL [<&MSVCR71.printf>]
004010B7 004010BA 004010BC
ADD ESP,8 PUSH 1 CALL [<&MSVCR71.exit>]
Figure 13.3 An unstructured control flow graph representing branches in the original program. The dotted arrows represent conditional branch instructions while the plain ones represent fall-through cases this is where execution proceeds when a branch isn t taken.
The control flow graph in Figure 13.3 is quite primitive. It is essentially a graphical representation of the low-level control flow statement in the program. It is important to perform this simple analysis at this early stage in decompilation to correctly break the program into basic blocks. The process of actually structuring these graphs into a representation closer to the one used by high-level languages is performed later, during the control flow analysis stage.