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13.2 INTEGERS
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s'(i)(n+1..0) c'(i)(n+1..0) Y(n 1..0)
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(n+2)-bit carry-save adder/subtractor
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s'(i+1)(n+1..0)
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c'(i+1)(n+1..0)
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SRT-2 carry-save divider: basic cell.
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Figure 13.16. The combinational circuit (Figure 13.15) implements the circuit of Table 13.2. An additional (not represented) p-bit subtractor generates Q q_pos 2 q_neg. Another additional (not represented) (n 1)-bit adder generates r( p) s0 ( p) c0 (p), that is, the decoded value of the nal remainder. Furthermore, a correction circuit, similar to that of Figure 13.6, is necessary if the condition sign(R) sign(X) is to hold. The cost and computation time of the carry-save basic cell of Figure 13.14 are given by Cdivision
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step (n)
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n:CAND2 Ccarry-save adder (n 2)
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(13:17)
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s'(n+1..n 2)
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c'(n+1..n 2)
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4-bit adder w''(3..0) Table 13.2
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q_pos, q_neg, en, op
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Figure 13.15 Selection of q _ pos, q _ neg,en,op.
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s'(0)(n+1..0)=X s'(0)(n+1..n 2) q_pos(p 1), q_neg(p 1) combin. circuit c'(0)(n+1..n 2) 0 s'(0)(n..0) en(p 1), op(p 1) division_step s'(1)(n+1..0) s'(1)(n+1..n 2) combin. circuit c'(1)(n+1..n 2) 0 s'(1)(n..0) en(p 2), op(p 2) division_step s'(2)(n+1..0) c'(2)(n+1..0) c'(1)(n..0) 0 c'(1)(n+1..0) c'(0)(n..0) 0 c'(0)(n+1..0)=0
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DIVIDERS
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Y(n 1..0)
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q_pos(p 2), q_neg(p 2)
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q_pos(0), q_neg(0)
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s'(p 1)(n+1..n 2) combin. circuit c'(p 1)(n+1..n 2) 0 s'(p 1)(n..0) en(0), op(0) division_step s'(p)(n+1..0) c'(p)(n+1..0) c'(p 1)(n..0) 0
SRT-2 carry-save divider: general structure.
and Tdivision
step
TAND2 Tcarry-save adder (1):
(13:18)
Observe that (Table 13.2) the control signals op and en can be chosen equal to op q neg and en q pos _ q neg, (13:19)
so that the circuit of Figure 13.15 can be synthesized with a 4-bit adder, a 4-input 2-output look-up table, and some additional logic gates. According to Comment
13.2 INTEGERS
TABLE 13.2 De nitions w00 0000 0001 0010 0011 0100 to 1010 1011 1100 1101 1110 1111 q _ pos 1 1 1 1 0 0 0 0 0 q _ neg 0 0 0 0 1 1 1 1 0 en 1 1 1 1 1 1 1 1 0 op 0 0 0 0 1 1 1 1
6.4, in some cases a 3-bit adder can be used. So, the cost and computation time of the circuit of Figure 13.15 are approximately equal to Ccomb:circuit Cadder (4) CLUT (4, 2) and Tcomb:circuit Tadder (4) TLUT (4, 2): (13:21) (13:20)
The cost and computation time of a carry-save SRT-2 divider, that is, Figure 13.16 with an additional (p 1)-bit subtractor for computing q _ pos 2 q _ neg, and an additional (n 1)-bit adder for computing r(p) s0 (p) c0 (p)), without the correction circuit, are given by C(n, p) p:Cdivision step (n) p:Ccomb:circuit Csubtractor (p 1) Cadder (n 1), and T(n, p) p:Tdivision step p:Tcomb:circuit max (Tsubtractor (p 1), Tadder (n 1)): Thus, the computation time is a linear (not quadratic) function of p and n. Example 13.8 (Complete VHDL source code available.) Generate a generic n-bit base-2 SRT divider with carry-save remainder. The correction cell is similar to that of Figure 13.8. The division step of Figure 13.14 is: (13:23) (13:22)
entity srt_cs_cell is port ( y: in std_logic_vector (N-1 downto 0);
432 s, c: in std_logic_vector (N+1 downto 0); en, op: in std_logic; next_s, next_c: out std_logic_vector (N+1 downto 0) ); end srt_cs_cell;
DIVIDERS
architecture behavioral of srt_cs_cell is signal op_y, sum: std_logic_vector (N+1 downto 0); signal cy: std_logic_vector (N+2 downto 0); begin process (en, op, y) begin if en= 0 then op _ y<=(others=> 0 ); else if op= 1 then op _ y<="00"&y; else op_ y <=("11"¬(y))+1; end if; end if; end process; adder: for i in 0 to N+1 generate sum(i)<=op_y(i) xor c(i) xor s(i); cy(i+1)<=(op_ y(i)and c(i))or(op_ y(i)and s(i))or(s(i)and c(i)); end generate; next_s<=sum; next_c<=cy(N+1 downto 1)& 0 ; end behavioral;
The combinational circuit of Figure 13.16 is:
entity srt_cs_selection is port ( s, c: in std_logic_vector (3 downto 0); en, op: out std_logic; q _ pos, q _ neg: out std_logic ); end srt_cs_selection; architecture behavioral of srt_cs_selection is signal t: std_logic_vector (3 downto 0); begin t<=s+c; process (t) begin case t is when "0000"|"0001"|"0010"|"0011"=> q _ pos<= 1 ; q _ neg<= 0 ; en<= 1 ; op<= 0 ; when "1011"|"1100"|"1101"|"1110"=> q _ pos<= 0 ; q _ neg<= 1 ; en<= 1 ; op<= 1 ;