r(p)(n 1..0)

TABLE 13.1 Selection of q _ pos(p-i-1), q _ neg(p-i-1), en(p-i-1), and op(p-i-1) r(i)(n 2 1) 0 0 1 1 r(i)(n 2 2) 0 1 0 1 q _ pos (p-i-1) 0 1 0 0 q _ neg (p-i-1) 0 0 1 0 en(p-i-1) 0 1 1 0 op(p-i-1) 1 0

be better than (or equivalent to) the SRT-2 method. The real advantage of the base-2 SRT algorithm is when stored-carry encoding is used (next section). Example 13.7 (Complete VHDL source code available.) Generate a generic n-bits base-2 SRT divider. The division step of Figure 13.12 is:

entity srt_cell is port ( r_by_2: in STD_LOGIC_VECTOR (N-1 downto 0); y: in STD_LOGIC_VECTOR (N-1 downto 0); en, op: in STD_LOGIC; r_n: out STD_LOGIC_VECTOR (N-1 downto 0) ); end srt_cell; architecture behavioral of srt_cell is begin cell: process (en,op,y,r_by_2) begin if en= 1 then if op= 1 then r_n<=r_by_2-y; else r_n<=r_by_2+y; end if; else r_n<=r_by_2; end if; end process; end behavioral;

The combinational circuit of Table 13.1 is:

entity comb_circ is port ( r: in STD_LOGIC_VECTOR (1 downto 0); q _ pos, q _ neg: out STD_LOGIC; en, op: out STD_LOGIC); end comb_circ; architecture behavioral of comb_circ is begin combinational: process (r) begin case r is when "00"=>q_pos<= 0 ; q_neg<= 0 ; when "01"=>q_pos<= 1 ; q_neg<= 0 ; when "10"=>q_pos<= 0 ; q_neg<= 1 ; when "11"=>q_pos<= 0 ; q_neg<= 0 ; when others=>NULL; end case; end process; end behavioral;

en<= 0 ; en<= 1 ; en<= 1 ; en<= 0 ;

op<= - ; op<= 1 ; op<= 0 ; op<= - ;

The divider structure of Figure 13.13 is:

entity SRT_radix2 is port ( X: in STD_LOGIC_VECTOR (N-1 downto 0); Y: in STD_LOGIC_VECTOR (N-1 downto 0); Q: out STD_LOGIC_VECTOR (P downto 0); R: out STD_LOGIC_VECTOR (N-1 downto 0) ); end SRT_radix2; architecture srt_arch of SRT_radix2 is type connect is array (0 to P) of STD_LOGIC_VECTOR (N downto 0); signal r_in, r_out: connect; signal QQ, Q _ pos, Q _ neg, en, op: STD_LOGIC_VECTOR (P downto 0); begin r_in(0)<=X& 0 ; divisor: for i in 0 to P-1 generate comb: comb_circ port map(r_in(i)(N downto N-1), Q _ pos(P-i-1), Q _ neg(P-i-1), en(P-i-1), op(P-i-1)); div_step: srt_cell port map (r_in(i)(N-1 downto 0), Y, en(P-i-1), op(P-i-1),r_out(i)(N-1 downto 0)); r_in(i+1)<=r_out(i)(N-1 downto 0)& 0 ; end generate; QQ<=( 0 &Q _ pos) - ( 0 &Q _ neg); nal_adjust: correction_cell port map (QQ, r_in(P)(N downto 1), Y, x_n=>X(N-1), r_in(P)(N), Q, R); end srt_arch;

13.2.3.2 SRT-2 Divider with Carry-Save Computation of the Remainder Let Y be an n-bit normalized number and X an integer belonging to the range 2Y X , Y, so that it can be expressed as an (n 1)-bit 2 s complement integer. Then Algorithm 6.8 can be applied. At each step the following operation is performed (recall that s0 and c0 stand for s/2 and c/2): (s0 (i 1) c0 (i 1)) 2:s0 (i) 2:c0 (i)) q(p i 1):Y, where s0 (i 1), c0 (i 1), s0 (i), and c0 (i) are (n 2)-bit 2 s complement numbers, Y is an n-bit natural number, and q(p 2 i 2 1) is a signed bit (21, 0 or 1) whose value is de ned (Figure 6.5 and Table 6.2) as a function of s(i)(n 2..n 2 1) and c(i)(n 2..n 2 1), that is, s0 (i)(n 1..n 2 2) and c0 (i)(n 1..n 2 2). The basic cell is shown in Figure 13.14. The carry-save adder is a set of full adders working in parallel ( 11), so that its computation time does not depend on the operand size. If en 0, then (s0 (i 1) c0 (i 1)) 2.s0 (i) 2. c0 (i)); if en 1 then (s0 (i 1) c0 (i 1)) 2.s0 (i) 2.c0 (i)) + Y, where the operation is selected by op (0: add; 1: subtract). The divider structure is shown in