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r(p)(n 1..0) conditional_adder
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remainder(n 1..0)
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Figure 13.9 Divider for normalized numbers.
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Example 13.5 (Complete VHDL source code available.) Generate the VHDL model of a divider for normalized base-2 numbers (Figure 13.9 with the basic cell of Figure 13.6):
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entity nr_cell is port ( a_by_2: in STD_LOGIC_VECTOR (N downto 0); b: in STD_LOGIC_VECTOR (N-1 downto 0);
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420 q: in STD_LOGIC; r: out STD_LOGIC_VECTOR (N downto 0) ); end nr_cell; architecture nr_cel_arch of nr_cell is begin adder_subtracter: process (q,a_by_2,b) begin if q= 1 then r<=a_by_2+b; else r<=a_by_2 - b; end if; end process; end nr_cel_arch;
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DIVIDERS
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The correction cell of Figure 13.8 (if necessary) is reduced to a conditional adder, and the last quotient bit (q(0)) is the negative of the last-remainder s most-signi cant-bit.
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entity cond_adder is port ( a: in STD_LOGIC_VECTOR (N-1 downto 0); b: in STD_LOGIC_VECTOR (N-1 downto 0); sel: in STD_LOGIC; r: out STD_LOGIC_VECTOR (N-1 downto 0) ); end cond_adder; architecture cond_adder_arch of cond_adder is begin conditional_adder: process (sel,a,b) begin if sel= 1 then r<=a+b; else r<=a; end if; end process;
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The divider structure of Figure 13.9 is:
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entity div_nr_norm is port ( X: in STD_LOGIC_VECTOR (N-1 downto 0); Y: in STD_LOGIC_VECTOR (N-1 downto 0); Q: out STD_LOGIC_VECTOR (P-1 downto 0); R: out STD_LOGIC_VECTOR (N-1 downto 0) ); end div_nr_norm;
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13.2 INTEGERS
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architecture div_arch of div_nr_norm is type connect is array (0 to P+1) of STD_LOGIC_VECTOR (N downto 0); Signal r_in, r_out: connect; Signal op: STD_LOGIC_VECTOR (P+1 downto 0); begin wires_in(0)<= 0 &X; op(0)<= 0 ; divisor: for i in 0 to P generate nr_step: nr_cell port map (r_in(i), b=>Y, op(i), r_out(i)); Q(P-i)<=not wires_out(i)(N); op(i+1)<=r_out(i)(N); r_in(i+1)<=r_out(i)(N-1 downto 0)& 0 ; end generate; rem_adj: cond_adder port map (r_out(P)(N-1 downto 0), Y, r_out(P)(N), R); end div_arch;
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Base-B Nonrestoring Divider
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Figure 13.10 depicts the basic cell corresponding to the non restoring base-B division step of Algorithm 6.10. It includes an 8-input 2-output look-up table (LUT), a 2-digit by n-digit multiplier, and an (n 2)-digit subtractor. The LUT inputs are rt, entered as the ve leftmost digits B.r(i)(n 1..n 2 3) of the shifted remainder, and Yt, entered as the three leftmost digits Y(n 2 1..n 2 3) of the divisor; the 2-digit output corresponds to the result qt of the integer division rt/Yt 1, namely the selected 2-digit quotient. The LUT size and cost can become prohibitive for increasing values of B, so a fast 5-digit by 3-digit base-B divider can be designed as an alternative. The
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r(i)(n..0) r(i)(n..n-4) Y(n-1..0) Y(n-1..n-3)
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8-input 2-output LUT
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qt1 qt0
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2xn-digit multiplier
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0 qt.Y
(n+2)-digit subtractor
r(i+1)
Base-B nonrestoring divider: basic cell.
DIVIDERS
multiplier output is the product qt.Y of the selected quotient by the divisor. According to the resources at hand those products may be precalculated then stored for fast retrieval. The subtractor computes the new remainder as the difference B.r(i) 2 qt.Y. Finally, a carry-save computation of r(i 1) could be implemented but conditions over the quotient-digit set have to be relaxed. The divider structure is shown in Figure 13.11. The cost and computation time of the nonrestoring divider basic cell of Figure 13.10 are given by Cdivision and Tdivision or Tdivision
step (n) step (n) step (n)
CLUT (8, 2) Cmultiplier (2 n) Csubtractor (n 2),
(13:8)
TLUT (8, 2) Tmultiplier (2 n) Tsubtractor (n 2),
(13:9)
TLUT (8, 2) Tmultiplier (2 n) Tfull adder Tsign-bit ,
(13:10)
if carry-save is implemented.
qt1(p-1) qt0(p-1)
division_step
r(0)=X r(1) r(i-1) Y
p-digit base-B
qt1(p-2) qt0(p-2)
base-B shift registers
division_step
qt1(p-i) qt0(p-i) (p-i) th division_step
adder
r(p-1) qt1(0) qt0(0)
r(i)
base-B register
p-digit base-B adder division_step
Clk' Clk
r(p)
Nonrestoring base-B divider: general structure.
13.2 INTEGERS
The cost and computation time of the non restoring base-B divider of Figure 13.11 are given by C(n, p) p:Cdivision and T(n, p) p:Tdivision
step (n) step (n)
Cadder (p),
(13:11)
Tadder (p):
(13:12)
Example 13.6 (Complete VHDL source code available.) Generate a generic ndigit base-B nonrestoring divider. The division step of Figure 13.10 is:
entity nr_baseB_step is port ( a: in digit_vector(N downto 0); b: in digit_vector(N-1 downto 0); q1, q0: out digit; r: out digit_vector(N downto 0) ); end nr_baseB_step; architecture behavioral of nr_baseB_step is signal rt: digit_vector(4 downto 0); signal yt: digit_vector(2 downto 0); signal qt1,qt0: digit; signal a_x_BASE, q_x_b, remainder: digit_vector(N downto 0); begin rt<=a(N downto N-4); yt<=b(N-1 downto N-3); a_x_BASE(N downto 1)<=a(N-1 downto 0); a_x_BASE(0)<=0; LookUpTable:look_up_table port map (rt, yt, qt1, qt0); mult: base_b_2_x_n_mult port map (qt1&qt0, B, q_x_b); subtractor: base_b_subt port map (a_x_BASE, q_x_b, remainder); q1<=qt1; q0<=qt0; r<=remainder; end behavioral;
The divider structure is:
entity div_nr_baseB is port ( A: in digit_vector(N-1 downto 0); B: in digit_vector(N-1 downto 0); Q: out digit_vector(P-1 downto 0); R: out digit_vector(N-1 downto 0) ); end div_nr_baseB;