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13.1 NATURAL NUMBERS
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2.r(0)=X 2m 1.Y
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Integer divider for natural operands.
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The VHDL model is based on Figure 13.3, taking into account the observation of Figure 13.4.
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entity div_rest_nat is port ( X: in STD_LOGIC_VECTOR (M-1 downto 0); Y: in STD_LOGIC_VECTOR (N-1 downto 0); Q: out STD_LOGIC_VECTOR (M-1 downto 0); R: out STD_LOGIC_VECTOR (N-1 downto 0) ); end div_rest_nat;
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n +1 bits 2.r (i ) 2m 1.Y 0 ... ... 0 m 1 bits ... ... 0 0
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DIVIDERS
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architecture div_arch of div_rest_nat is type connect is array (0 to M-1) of STD_LOGIC_VECTOR (N downto 0); signal wires_in, wires_out: connect; signal zeros: STD_LOGIC_VECTOR (N-1 downto 0); begin zeros<=(others=> 0 ); wires_in(0)<=zeros&X(M-1); divisor: for i in 0 to M-1 generate rest_cell: restoring_cell port map (wires_in(i), Y, Q(M-i-1), wires_out(i)(N-1 downto 0)); end generate; wires_conections: for i in 0 to M-2 generate wires_in(i+1)<=wires_out(i)(N-1 downto 0)&X(M-i-2); end generate; R<=wires_out(M-1)(N-1 downto 0); end div_arch;
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In non binary cases the division_step block is more complex. The base-B division step described in Algorithm 6.3 consists of checking increasing values of the quotient-digit q up to the minimum value verifying B:a , q:b, (13:3)
where B.a and b are the shifted remainder and the divisor, respectively; if qmin is the minimum value of q verifying (13.3), then qmin21 is the asserted quotient-digit. This method is easy but quite ineffective. The restoring base-B division step described by Algorithm 6.4 is faster because only one value of q has to be checked at every step. The corresponding circuit is shown in Figure 13.5. It includes a 5-input 2-output look-up table, an (n 1)-digit multiplier, an (n 1)-digit subtractor, an n-digit adder, and (n 1) 2-to-1 multiplexers. As far as B is greater than 2, the n-digit adder may not be replaced by a direct connection of a to the inputs 1 of the (n 1) 2-to-1 multiplexers; in this case the restoring process doesn t actually restore the previous remainder, but consists of adding one divisor to a negative new remainder. The adding stage could be nevertheless eliminated if two subtractions are executed in parallel (2qt.b and 2(qt 2 1).b); then the multiplexers would select the correct remainder according to the sign of the result. This would provide a saving in cycle time, without signi cantly increasing the hardware cost.
13.1 NATURAL NUMBERS
a a(n 1.. n 3) b(n 1.. n 2) b
look-up table q 1 0 qt-1 qt
sign
(n+1)-digit subtractor
n-digit adder
Figure 13.5 Basic cell of a nonbinary divider.
The cost and the computation time of the corresponding divider are, respectively, C(n, p) p:(CLUT (5, 2) Cmultiplier (n 1) Csubtractor (n 1) Cadder (n) (n 1):Cmux ) and T(n, p) p:(TLUT (5, 2) Tmultiplier (n 1) Tsubtractor (n 1) Tadder (n) Tmux ): (13:5) (13:4)
Example 13.3 (Complete VHDL source code available.) Generate a generic n-digits base-B restoring divider. The division step of Figure 13.5 is:
entity rest_baseB_step is port ( a: in digit_vector(N-1 downto 0); b: in digit_vector(N-1 downto 0);
414 q: out digit; r: out digit_vector(N-1 downto 0) ); end rest_baseB_step;
DIVIDERS
architecture behavioral of rest_baseB_step is signal at: digit_vector(2 downto 0); signal bt: digit_vector(1 downto 0); signal qt, qt_1: digit; signal q_x_b, a_x_B, re, r_plus_b: digit_vector(N downto 0); signal sign: bit; begin at<=a(N-1 downto N-3); bt<=b(N-1 downto N-2); a_x_B(N downto 1)<=a; a_x_B(0)<=0; LUT: look_up_table port map(at, bt, qt, qt_1); mult: base_b_mult port map(qt, B, q_x_b); subt: base_b_subt port map(a_x_B, q_x_b, re, sign); adder: base_b_adder port map(re(N-1 downto 0), B, r_plus_b); multiplexers: process (sign,qt_1, qt, r_plus_b,re) begin if sign= 1 then q<=qt_1; r<=r_plus_b(N-1 downto 0); else q<=qt; r<=re(N-1 downto 0); end if; end process; end behavioral;
The divider structure is:
entity div_rest_baseB is port ( A: in digit_vector(N-1 downto 0); B: in digit_vector(N-1 downto 0); Q: out digit_vector(P-1 downto 0); R: out digit_vector(N-1 downto 0) ); end div_rest_baseB; architecture div_arch of div_rest_baseB is type connections is array (0 to P) of digit_vector(N-1 downto 0); Signal wires: connections; begin wires(0)<=A; divisor: for i in 0 to P-1 generate rest_step: rest_baseB_step port map (wires(i), B, Q(P-i-1), wires(i+1)); end generate;