Top-Level Module for the SRC Processor in VS .NET

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Appendix
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Top-Level Module for the SRC Processor
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The module de ned in this appendix belongs to the SRC processor example of 17.
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module SrcProcessor( output hasExecutedStop, output [31:0] memory_Port1_DataIn, output [31:0] memory_Port1_AddressIn, output memory_Port1_WriteStrobe, output [31:0] memory_Port2_DataIn, output [31:0] memory_Port2_AddressIn, output memory_Port2_WriteStrobe, output [31:0] registerFile_Port1_DataIn, output [4:0] registerFile_Port1_AddressIn, output registerFile_Port1_WriteStrobe, output [31:0] registerFile_Port2_DataIn, output [4:0] registerFile_Port2_AddressIn, output registerFile_Port2_WriteStrobe, output [31:0] registerFile_Port3_DataIn, output [4:0] registerFile_Port3_AddressIn, output registerFile_Port3_WriteStrobe, output [31:0] registerFile_Port4_DataIn, output [4:0] registerFile_Port4_AddressIn, output registerFile_Port4_WriteStrobe, input clock, input srcProcessorReset, input canRun, input [31:0] memory_Port1_DataOut, input [31:0] memory_Port2_DataOut, input [31:0] registerFile_Port1_DataOut, input [31:0] registerFile_Port2_DataOut, input [31:0] registerFile_Port3_DataOut, input [31:0] registerFile_Port4_DataOut,
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Advanced FPGA Design. By Steve Kilts Copyright # 2007 John Wiley & Sons, Inc.
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Appendix B input enableForwarding, input [31:0] cycleNumber); wire hasDecodedStop; wire hasExecutedStop; // Stage1 declarations wire [31:0] intoStage1_PC; wire [31:0] intoStage1_IR; wire stage2IsStalled; wire intoStage1_CanRun; wire intoStage1_ShouldStop; wire fromStage2_BranchIsTaken; wire [31:0] fromStage1_PC; wire [31:0] fromStage1_IR; wire [31:0] fromStage1_NextPC; wire stage1IsStalled; // Stage2 declarations wire [31:0] intoStage2_PC; wire [31:0] intoStage2_IR; wire [31:0] intoStage2_NextPC; wire [31:0] fromStage2_PC; wire [31:0] fromStage2_IR; wire [31:0] fromStage2_DecodedIR; wire [31:0] fromStage2_X; wire [31:0] fromStage2_Y; wire [31:0] fromStage2_MD; wire fromStage2_IsRegisterWrite; wire [4:0] fromStage2_Ra; wire [31:0] fromStage2_NextPC; wire fromStage2_IsStop; wire [4:0] ra; wire [31:0] contentsRaFromRegisterFile; wire [4:0] rb; wire [31:0] contentsRbFromRegisterFile; wire [4:0] rc; wire [31:0] contentsRcFromRegisterFile; wire isRegisterWriteInStage3; wire [4:0] raInStage3; wire [31:0] contentsRaFromStage3; wire contentsRaFromStage3Ready; wire isRegisterWriteInStage4; wire [4:0] raInStage4; wire [31:0] contentsRaFromStage4; wire contentsRaFromStage4Ready; wire isRegisterWriteInStage5; wire [4:0] raInStage5; wire [31:0] contentsRaFromStage5; wire contentsRaFromStage5Ready; wire enableForwarding;
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Appendix B // Stage3 declarations wire [31:0] intoStage3_PC; wire [31:0] intoStage3_IR; wire [31:0] intoStage3_DecodedIR; wire [31:0] intoStage3_X; wire [31:0] intoStage3_Y; wire [31:0] intoStage3_MD; wire intoStage3_IsRegisterWrite; wire [4:0] intoStage3_Ra; wire [31:0] fromStage3_PC; wire [31:0] fromStage3_IR; wire [31:0] fromStage3_DecodedIR; wire [31:0] fromStage3_Z; wire [31:0] fromStage3_MD; wire fromStage3_IsRegisterWrite; wire [4:0] fromStage3_Ra; // Stage4 declarations wire [31:0] intoStage4_PC; wire [31:0] intoStage4_IR; wire [31:0] intoStage4_DecodedIR; wire [31:0] intoStage4_Z; wire [31:0] intoStage4_MD; wire intoStage4_IsRegisterWrite; wire [4:0] intoStage4_Ra; wire [31:0] fromStage4_PC; wire [31:0] fromStage4_IR; wire [31:0] fromStage4_DecodedIR; wire [31:0] fromStage4_Z; wire fromStage4_IsRegisterWrite; wire [4:0] fromStage4_Ra; wire [31:0] toDataMemory_Address; wire [31:0] toDataMemory_Data; wire toDataMemory_WriteStrobe; wire [31:0] fromDataMemory_Data; // Stage5 declarations wire [31:0] intoStage5_PC; wire [31:0] intoStage5_IR; wire [31:0] intoStage5_DecodedIR; wire [31:0] intoStage5_Z; wire intoStage5_IsRegisterWrite; wire [4:0] intoStage5_Ra; wire fromStage5_IsStop; wire [4:0] toRegisterFile_Address; wire [31:0] toRegisterFile_Data; wire toRegisterFile_WriteStrobe; // unused but included here for completeness wire [31:0] fromRegisterFile_Data;
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Appendix B // logic for interface to instruction and data memory assign intoStage1_IR = memory_Port1_ DataOut; assign memory_Port1_DataIn = 32 b0; assign memory_Port1_AddressIn = intoStage1_PC; assign memory_Port1_WriteStrobe = 1 b0; assign assign assign assign fromDataMemory_Data memory_Port2_DataIn memory_Port2_AddressIn memory_Port2_WriteStrobe = memory_Port2_ DataOut; = toDataMemory_ Data; = toDataMemory_ Address; = toDataMemory_ WriteStrobe;
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// logic for interface to register file assign contentsRaFromRegisterFile = registerFile_ Port1_DataOut; assign registerFile_Port1_DataIn = 32 b0; assign registerFile_Port1_AddressIn = ra; assign registerFile_Port1_WriteStrobe = 1 b0; assign assign assign assign assign assign assign assign assign assign assign assign = registerFile_ Port2_DataOut; registerFile_Port2_DataIn = 32 b0; registerFile_Port2_AddressIn = rb; registerFile_Port2_WriteStrobe = 1 b0; = registerFile_ Port3_DataOut; registerFile_Port3_DataIn = 32 b0; registerFile_Port3_AddressIn = rc; registerFile_Port3_WriteStrobe = 1 b0; = registerFile_ Port4_DataOut; registerFile_Port4_DataIn = toRegisterFile_ Data; registerFile_Port4_AddressIn = toRegisterFile_ Address; registerFile_Port4_WriteStrobe = toRegisterFile_ WriteStrobe; fromRegisterFile_Data contentsRcFromRegisterFile contentsRbFromRegisterFile
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// // Module: FeedbackDRegisterWith2Inputs // // Description: // Special register for PC
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Appendix B // // Inputs: // clk // shouldHold // d0 // d1 // select // reset // resetValue // // Outputs: // q //
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clock stage1IsStalled fromStage1_NextPC fromStage2_NextPC fromStage2_BranchIsTaken srcProcessorReset
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--> intoStage1_PC
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FeedbackDRegisterWith2Inputs #(32, 5, 0, 0) PC ( clock, stage1IsStalled, fromStage1_NextPC, fromStage2_NextPC, fromStage2_BranchIsTaken, intoStage1_PC, srcProcessorReset, 32 b0); or IntoStage1_ShouldStop ( intoStage1_ShouldStop, hasDecodedStop, fromStage2_IsStop); = canRun;
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assign // // // // // // // // // // // // // // // // // //
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intoStage1_CanRun
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Module: Stage1 Description: Instruction Fetch Inputs: inputPC inputIR stage2IsStalled canRun shouldStop branchIsTakenInStage2 Outputs: outputPC outputIR outputNextPC
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intoStage1_PC intoStage1_IR stage2IsStalled intoStage1_CanRun intoStage1_ShouldStop fromStage2_BranchIsTaken
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--> fromStage1_PC --> fromStage1_IR --> fromStage1_NextPC
Appendix B // // stage1IsStalled --> stage1IsStalled
Stage1 stage1 (intoStage1_PC, intoStage1_IR, stage2IsStalled, intoStage1_CanRun, intoStage1_ShouldStop, fromStage2_BranchIsTaken, fromStage1_PC, fromStage1_IR, fromStage1_NextPC, stage1IsStalled); // // // // // // // // // // // // // // // // Module: FeedbackDRegisterWith1Input Description: Registers for interface between stage 1 and stage 2 Inputs: clk shouldHold d reset resetValue Outputs: q