Figure 18.2 Elements of timing analysis. in .NET

Creator European Article Number 13 in .NET Figure 18.2 Elements of timing analysis.
Figure 18.2 Elements of timing analysis.
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18.1 Standard Analysis
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Figure 18.3 Positive slack.
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have negative slack and will not meet timing. Setup analysis also applies to I/O. For an input, the launch clock-to-Q and external prop time are lumped into a single external delay for the analysis. Similarly, the output setup analysis will assume a single external prop time that includes the setup time and clock skew. Because these external delays are unknown to the FPGA timing analysis tool, they must be de ned by the designer. Hold violations occur when data arrives at a ip- op too soon after the rising edge of the clock and are relatively easy to x by adding additional buffering. Hold delay violations are rare in FPGA designs due to the built-in delay of the routing matrix. If a hold violation occurs, it usually indicates a clock skew problem. In addition to de ning accurate constraints for the system clocks, it is also important to de ne any path constraints that can be relaxed. The two most common constraints that fall into this category are multicycle and false paths. The multicycle path is illustrated in Figure 18.4.
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Figure 18.4 Multicycle path.
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18 Static Timing Analysis
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The multicycle path allows constrained signals n-cycles to propagate between timing end points. Note that even with a multicycle path, the setup and hold requirements are still in effect. This is because regardless of which clock edge the data arrives at, if it arrives too close to the clock edge, a metastable condition could still occur. A multicycle path may be added as a constraint if the data does not need to be used in the immediately following clock period. This could occur when interfacing to devices that do not require the immediate arrival of the data. This often occurs in DSP applications where there is a xed sampling rate and an available number of clocks per sample. A false path is similar to the multicycle path in that it is not required to propagate signals within a single clock period. The difference is that a false path is not logically possible as dictated by the design. In other words, even though the timing analysis tool sees a physical path from one point to the other through a series of logic gates, it is not logically possible for a signal to propagate between those two points during normal operation. This is illustrated in Figure 18.5. Because the path will never be traversed during normal operation of the design, the static timing analysis tool ignores the path between these points and is not considered during timing optimization and critical-path analysis. The main difference between a multicycle path with many available cycles (large n) versus a false path is that the multicycle path will still be checked against setup and hold requirements and will still be included in the timing analysis. It is possible for a multicycle path to still fail timing, but a false path will never have any associated timing violations.
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It is possible for a multicycle path to fail timing even with an arbitrarily high cycle constraint, but it is not possible for false paths to fail timing.
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Once these constraints are in place, the STA tool can run a comprehensive analysis of every path in the design. There are a number of advantages of static timing analysis over simulation-based dynamic timing analysis as discussed in previous chapters:
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Dynamic timing analysis (simulations with timing information) will only catch a few problems. The utility of dynamic analysis is only as good as
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Figure 18.5 False path.
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18.2 Latches
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the person that wrote the simulation. STA, on the other hand, will catch all problems within the bounds of standard timing analysis. In other words, STA performs an exhaustive analysis on the design. The only requirement for the designer is to set up the necessary conditions and constraints.
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It is hard to model characteristics such as jitter, as this would create a very complex testbench and push the run times to unreasonable levels. With STA, combinations of various conditions can be veri ed with a proportional increase in run time. With dynamic timing analysis, combinations of various conditions can push the run time out exponentially. STA does not require any simulation cycles, and there is no overhead due to event schedulers. STA provides a larger scope of timing violations including positive and negative setup/hold, min and max transition, clock skew, glitch detection, and bus contention. STA tools have the ability to automatically detect and identify critical paths, violations, and asynchronous clocks.
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The dif culty with STA arises when structures that are not well suited for STA are analyzed in this environment. Because of these constraints, dynamic timing analysis is often used to analyze these structures. The following sections discuss some of the more complex topologies in more detail and recommend methods to analyze these structures. Note that many of these structures are uncommon and are typically not recommended for FPGA designs. Listing these structures is not an endorsement to use them, but if an FPGA designer has good reason, then the suggestions can be used to analyze these successfully.
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