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This chapter discusses the second of three primary physical characteristics of
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a digital design: area. Here we also discuss methods for architectural area optimization in an FPGA. We will discuss area reduction based on choosing the correct topology. Topology refers to the higher-level organization of the design and is not device speci c. Circuit-level reduction as performed by the synthesis and layout tools refers to the minimization of the number of gates in a subset of the design and may be device speci c. A topology that targets area is one that reuses the logic resources to the greatest extent possible, often at the expense of throughput (speed). Very often this requires a recursive data ow, where the output of one stage is fed back to the input for similar processing. This can be a simple loop that ows naturally with the algorithm or it may be that the logic reuse is complex and requires special controls. This section describes both techniques and describes the necessary consequences in terms of performance penalties. During the course of this chapter, we will discuss the following topics in detail:
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. . .
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Rolling up the pipeline to reuse logic resources in different stages of a computation. Controls to manage the reuse of logic when a natural ow does not exist. Sharing logic resources between different functional operations. The impact of reset on area optimization. Impact of FPGA resources that lack reset capability. Impact of FPGA resources that lack set capability. Impact of FPGA resources that lack asynchronous reset capability. Impact of RAM reset. Optimization using set/reset pins for logic implementation.
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Advanced FPGA Design. By Steve Kilts Copyright # 2007 John Wiley & Sons, Inc.
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ROLLING UP THE PIPELINE
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The method of rolling up the pipeline is the opposite operation to that described in the previous chapter to improve throughput by unrolling the loop to achieve maximum performance. When we unrolled the loop to create a pipeline, we also increased the area by requiring more resources to hold intermediate values and replicating computational structures that needed to run in parallel. Conversely, when we want to minimize the area of a design, we must perform these operations in reverse; that is, roll up the pipeline so that logic resources can be reused. Thus, this method should be used when optimizing highly pipelined designs with duplicate logic in the pipeline stages.
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Rolling up the pipeline can optimize the area of pipelined designs with duplicated logic in the pipeline stages.
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Consider the example of a xed-point fractional multiplier. In this example, A is represented in normal integer format with the xed point just to the right of the LSB, whereas the input B has a xed point just to the left of the MSB. In other words, B scales A from 0 to 1.
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module mult8( output [7:0] input [7:0] input [7:0] input reg [15:0]
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product, A, B, clk); prod16;
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assign product = prod16[15:8]; always @(posedge clk) prod16 <= A * B; endmodule
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With this implementation, a new product is generated on every clock. There isn t an obvious pipeline in this design as far as distinct sets of registers, but note that the multiplier itself is a fairly long chain of logic that is easily pipelined by adding intermediate register layers. It is this multiplier that we wish to roll up. We will roll this up by performing the multiply with a series of shift and add operations as follows:
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module mult8( output output reg [7:0] input [7:0] input [7:0] input input reg [4:0]
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done, product, A, B, clk, start); multcounter; // counter for number of shift/adds
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2.1 Rolling Up the Pipeline reg reg [7:0] shiftB; // shift register for B [7:0] shiftA; // shift register for A
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wire adden; // enable addition assign adden = shiftB[7] & !done; assign done = multcounter[3]; always @(posedge // increment if(start) else if(!done) clk) begin multiply counter for shift/add ops multcounter <= 0; multcounter <= multcounter + 1;
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// shift register for B if(start) shiftB <= B; else shiftB[7:0] <= {shiftB[6:0], 1 b0}; // shift register for A if(start) shiftA <= A; else shiftA[7:0] <= {shiftA[7], shiftA[7:1]}; // calculate multiplication if(start) product <= 0; else if(adden) product <= product + shiftA; end endmodule
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The multiplier is thus architected with an accumulator that adds a shifted version of A depending on the bits of B as shown in Figure 2.1. Thus, we completely eliminate the logic tree necessary to generate a multiply within a single clock and replace it with a few shift registers and an adder. This is a very compact form of a multiplier but will now require 8 clocks to complete a multiplication. Also note that no special controls were necessary to sequence through this multiply operation. We simply relied on a counter to tell us when to stop the shift and add operations. The next section describes situations where this control is not so trivial.