Decision Trees in VS .NET

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12.1 Decision Trees
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Figure 12.6 Encoding for default condition.
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module regwrite( output reg rout, input clk, input [3:0] in, input [3:0] ctrl); always @(posedge clk) begin rout <= 0; case(1) ctrl[0]: rout <= in[0]; ctrl[1]: rout <= in[1]; ctrl[2]: rout <= in[2]; ctrl[3]: rout <= in[3]; endcase end endmodule
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This type of coding style eliminates the need for a default case and also ensures that the register is assigned to the default value if no other assignment is de ned. A synthesis directive similar to the parallel_case statement is the full_case directive. This directive informs the synthesis tool that all cases have been covered and that an implied default condition is not required. In general, the full_case directive is dangerous and can create a number of traps leading to incorrect or inef cient synthesis as well as mismatches with simulation.
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Use of the full_case directive is generally bad design practice.
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Full conditions can be designed with proper coding styles that completely avoid this directive as shown in the following example.
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12 Coding for Synthesis
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The full_case directive can be added in a similar way to the parallel_case directive as shown in the following example.
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// DANGEROUS CASE STATEMENT case(1) // synthesis full_case
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Figure 12.7 illustrates the implementation with this directive. The full_case statement tells the synthesis tool that all possible conditions have been covered by the case statement regardless of how the tool interprets the conditions. This implies that a default condition such as holding its current value is not necessary. As can be seen from the above implementation, all logic for maintaining the current value has been removed. All cases are assumed to be covered, and thus the only logic remaining is the mux itself. The full_case directive, like the parallel_case directive, is synthesis-only meaning that it will be ignored by simulation. This makes the full_case directive dangerous in that mismatches between simulation and synthesis may occur. Speci cally, if an output value is not provided by each condition, the simulation tool will latch the current value, whereas the synthesis tool will consider this a don t care.
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Parallel_case and full_case can cause mismatches between simulation and synthesis.
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The recommended approach is to avoid this constraint and to guarantee full coverage by design; that is, by using a default condition and setting default values prior to the case statement as shown above. This will make the code more portable and reduce the possibility of undesirable mismatches. One of the biggest dangers when setting FPGA synthesis options is the allowance of a default setting whereby all case statements are automatically assumed to be full_case, parallel_case, or both. It is quite frankly shocking that any vendors actually provide this as an option. In practice, this option should never be used. This type of option only creates hidden dangers in the form of improperly
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Figure 12.7 No default condition.
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12.1 Decision Trees
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synthesized code that may not be discovered with basic in-system testing and certainly not in simulation.
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Multiple Control Branches
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One common mistake (in the form of a poor coding style) is to disconnect the control branches for a single register. In the following example, oDat is assigned to two different values in two unique decision trees.
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// BAD CODING STYLE module separated( output reg oDat, input iClk, input iDat1, iDat2, iCtrl1, iCtrl2); always @(posedge iClk) begin if(iCtrl2) oDat <= iDat2; if(iCtrl1) oDat <= iDat1; end endmodule
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Because there is no way to tell if iCtrl1 and iCtrl2 are mutually exclusive, this coding is ambiguous, and the synthesis tool must make certain assumptions for the implementation. Speci cally, there is no explicit way to handle the priority when both conditions are true simultaneously. Thus, the synthesis tool must assign a priority based on the sequence in which these conditions occur. In this case, if the condition appears last, it will take priority over the rst. Based on Figure 12.8, iCtrl1 has priority over iCtrl2. If the order of these is swapped, the priority will likewise be swapped. This is the opposite behavior of an if/else structure that will give priority to the rst condition.
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