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case(1) ctrl[0]: ctrl[1]: ctrl[2]: ctrl[3]: endcase
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rout rout rout rout
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<= <= <= <=
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in[0]; in[1]; in[2]; in[3];
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Due to the fact that the case statement is available as an alternative to the if/else structure, many novice designers assume that this will implement a priority-less decision tree automatically. This happens to be true for the more rigorous language VHDL but is not the case for Verilog as can be seen in the implementation of the case statement in Figure 12.4. As can be seen in Figure 12.4, the default is such that the priorities are encoded to set the appropriate enable pins on the mux. This leads many designers into a trap. To remove the priority encoding, it is possible to use the synthesis
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Figure 12.4 Priority-encoded logic.
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12.1 Decision Trees
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directive parallel_case to implement a truly parallel structure. The syntax shown below will work with Synplicity and XST synthesis tools.
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// DANGEROUS CASE STATEMENT case(1) // synthesis parallel_case
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This directive can typically be added to the synthesis constraints. If this directive is used, it is certainly better to add it to the constraints so it is not hidden in the code if the designer needs to port to a new tool. This directive informs the synthesis tool that the cases are mutually exclusive and that it may forego any priority encoding as shown in Figure 12.5. Here, all inputs are selected based on enable bits that are assumed to be mutually exclusive. This implementation is faster and consumes less logic resources. Note that the parallel_case directive is a synthesis-only directive, and thus mismatches between simulation and actual implementation can occur. Frequent use of synthesis directives in general is bad design practice. It is better to code the RTL such that both the synthesis and simulation tools recognize the parallel architecture.
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Use of the parallel_case directive is generally bad design practice.
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Good coding practice dictates that priority encoders should be implemented with if/else statements, and structures that are parallel by design should be coded with case statements. There is typically no good reason to use the parallel_case
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Figure 12.5 No priority encoding.
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12 Coding for Synthesis
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directive. Some designers can successfully use these statements to optimize one-hot decoders, but because of the risks involved it is better to never use these statements at all. If the synthesis tool reports that the case structure is not parallel, then the RTL must be changed to make it so. If it is truly a priority condition, then an if/else should be used in its place.
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Full Conditions
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In the decision trees examined thus far, if none of the conditions of a case statement were true, the synthesis tool has fed the output of the register back around to the decision tree as a default condition (this behavior will of course depend on the default implementation style of the synthesis tool, but for this section we will assume it is true). Even with the full_case implementation, there is logic that will disable the register if none of the selection bits are asserted. The assumption is that if no conditions are met, the value does not change. One option available to the designer is to add a default condition. This may or may not be the current value, but it avoids the condition where the tool automatically latches the current value assuming that the output is assigned a value under each case condition. The register enable will be eliminated with this default condition as shown in the following modi cation to the case statement.
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// DANGEROUS CASE STATEMENT module regwrite( output reg rout, input clk, input [3:0] in, input [3:0] ctrl); always @(posedge clk) case(1) // synthesis parallel_case ctrl[0]: rout <= in[0]; ctrl[1]: rout <= in[1]; ctrl[2]: rout <= in[2]; ctrl[3]: rout <= in[3]; default: rout <= 0; endcase endmodule
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As can be seen in Figure 12.6, the default condition is now explicit and is implemented as an alternative input to the mux. Although the ip- op no longer requires an enable, the total logic resources have not necessarily decreased. Also note that if not every condition de nes an output for the register (this often occurs when multiple outputs are assigned within a single case statement), neither a default condition nor any synthesis tag will prevent the creation of a latch. To ensure that a value is always assigned to the register, an initial assignment can be used to assign a value to the register prior to the case statement. This is shown in the following example.
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