Coding for Synthesis in .NET

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Coding for Synthesis
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At the level of abstraction where logic is coded in an HDL language, synthesis
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optimizations can only take a designer so far when meeting design requirements. At its very fundamental level, a synthesis tool will follow the coding structure and map the logic according to the architecture laid out in the RTL. Only for very regular structures such as FSMs, RAMs, and so forth can a synthesis tool extract the functionality, identify alternative architectures, and implement accordingly. Aside from optimization, a fundamental guiding principle when coding for synthesis is to minimize, if not eliminate, all structures and directives that could potentially create a mismatch between simulation and synthesis. A good coding style typically ensures that the RTL simulation will behave the same as the synthesized netlist. One class of deviations are the vendor-supplied directives that can be added to the RTL code in the form of special comments (that are ignored by the simulation tool) that will cause the synthesis tool to interpret a logic structure in a way that is not obvious from the RTL code itself. During the course of this chapter, we will discuss the following topics:
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Creating ef cient decision trees. Trade-offs between priority and parallel structures Dangers of the parallel_case and full_case directives Dangers of multiple control branches Coding style traps. Usage of blocking and nonblocking assignments Proper and improper usage of for-loops Inferrence of combinatorial loops and latches
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Design partitioning and organization. Organizing data path and control structures Modular design
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Parameterizing a design for reuse.
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Advanced FPGA Design. By Steve Kilts Copyright # 2007 John Wiley & Sons, Inc.
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12 Coding for Synthesis
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12.1 DECISION TREES
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In the context of FPGA design, we refer to a decision tree as the sequence of conditions that are used to decide what action the logic will take. Usually, this breaks down to if/else and case structures. Consider a very simple register write example:
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module regwrite( output reg rout, input clk, input [3:0] in, input [3:0] ctrl); always @(posedge clk) if(ctrl[0]) rout else if(ctrl[1]) rout else if(ctrl[2]) rout else if(ctrl[3]) rout endmodule <= <= <= <= in[0]; in[1]; in[2]; in[3];
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This type of if/else structure can be conceptualized according to the mux structure shown in Figure 12.1. This type of decision structure could be implemented in a number of different ways depending on speed/area trade-offs and required priority. This section describes how various decision trees can be coded and constrained to target different synthesized architectures.
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Priority Versus Parallel
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Inherent in the if/else structure is the concept of priority. Those conditions that occur rst in the if/else statement are given priority over others in the tree. A higher priority with the structure above would correspond with the muxes near the end of the chain and closer to the register.
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Simple priority with serialized mux structure.
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12.1 Decision Trees
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Figure 12.2 Priority placement.
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In Figure 12.2, if bit 0 of the control word is set, in[0] will be registered regardless of the state of the other bits of the control word. If bit 0 of the control word is not set, then the states of the other bits are used to determine the signal that is passed to the register. In general, a bit will only be used to select the output if all bits ahead of it (in this case the LSBs) are not set. This is true of the priority mux implementation shown in Figure 12.3. Regardless of the nal implementation of the if/else structure, a higher priority is given to the conditional statements that occur previous to any given condition.
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If/else structures should be used when the decision tree has a priority encoding.
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Case structures, on the other hand, are often (but not always) used in circumstances where all conditions are mutually exclusive. In other words, they can be used to optimize the decision tree when only one condition can be true at any given time. For instance, when making a decision based on the value of some
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Figure 12.3 Priority mux.
12 Coding for Synthesis
other multibit net or register (say for an address decoder), only one condition can be true at one time. This is true of the decode operation that is implemented above with an if/else structure. To implement the exact same functionality in Verilog, a case statement can be used: