always @(posedge clk) begin rA <= A; rB <= B; rC <= C; Sum <= rA + rB + rC; end endmodule in VS .NET

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always @(posedge clk) begin rA <= A; rB <= B; rC <= C; Sum <= rA + rB + rC; end endmodule
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The rst register stage consists of rA, rB, and rC, and the second stage consists of Sum. The logic between stages 1 and 2 is the adder for all inputs, whereas the logic between the input and the rst register stage contains no logic (assume the outputs feeding this module are registered) as shown in Figure 1.9. If the critical path is de ned through the adder, some of the logic in the critical path can be moved back a stage, thereby balancing the logic load between the two register stages. Consider the following modi cation where one of the add operations is moved back a stage:
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module adder( output reg [7:0] input [7:0] input reg [7:0]
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Sum, A, B, C, clk); rABSum, rC;
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1 Architecting Speed always @(posedge clk) begin rABSum <= A + B; rC <= C; Sum <= rABSum + rC; end endmodule
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We have now moved one of the add operations back one stage between the input and the rst register stage. This balances the logic between the pipeline stages and reduces the critical path as shown in Figure 1.10.
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Register balancing improves timing by moving combinatorial logic from the critical path to an adjacent path.
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Reorder Paths
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The fth strategy is to reorder the paths in the data ow to minimize the critical path. This technique should be used whenever multiple paths combine with the critical path, and the combined path can be reordered such that the critical path can be moved closer to the destination register. With this strategy, we will only be concerned with the logic paths between any given set of registers. Consider the following module:
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module randomlogic( output reg [7:0] Out, input [7:0] A, B, C, input clk, input Cond1, Cond2); always @(posedge clk) if(Cond1) Out <= A; else if(Cond2 && (C < 8)) Out <= B; else Out <= C; endmodule
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Figure 1.10 Registers balanced.
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1.3 Timing
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Figure 1.11 Long critical path.
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In this case, let us assume the critical path is between C and Out and consists of a comparator in series with two gates before reaching the decision mux. This is shown in Figure 1.11. Assuming the conditions are not mutually exclusive, we can modify the code to reorder the long delay of the comparitor:
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module randomlogic( output reg [7:0] Out, input [7:0] A, B, C, input clk, input Cond1, Cond2); wire CondB = (Cond2 & !Cond1); always @(posedge clk) if(CondB && (C < 8)) Out <= B; else if(Cond1) Out <= A; else Out <= C; endmodule
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By reorganizing the code, we have moved one of the gates out of the critical path in series with the comparator as shown in Figure 1.12. Thus, by paying careful
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Figure 1.12 Logic reordered to reduce critical path.
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1 Architecting Speed
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attention to exactly how a particular function is coded, we can have a direct impact on timing performance.
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Timing can be improved by reordering paths that are combined with the critical path in such a way that some of the critical path logic is placed closer to the destination register.
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SUMMARY OF KEY POINTS
A high-throughput architecture is one that maximizes the number of bits per second that can be processed by a design. Unrolling an iterative loop increases throughput. The penalty for unrolling an iterative loop is a proportional increase in area. A low-latency architecture is one that minimizes the delay from the input of a module to the output. Latency can be reduced by removing pipeline registers. The penalty for removing pipeline registers is an increase in combinatorial delay between registers. Timing refers to the clock speed of a design. A design meets timing when the maximum delay between any two sequential elements is smaller than the minimum clock period. Adding register layers improves timing by dividing the critical path into two paths of smaller delay. Separating a logic function into a number of smaller functions that can be evaluated in parallel reduces the path delay to the longest of the substructures. By removing priority encodings where they are not needed, the logic structure is attened, and the path delay is reduced. Register balancing improves timing by moving combinatorial logic from the critical path to an adjacent path. Timing can be improved by reordering paths that are combined with the critical path in such a way that some of the critical path logic is placed closer to the destination register.