MIXING RESET TYPES 10.2.1 Nonresetable Flip-Flops in Visual Studio .NET

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10.2 MIXING RESET TYPES 10.2.1 Nonresetable Flip-Flops
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As a matter of good design practice, ip- ops of different reset types should not be combined into a single always block. The following code illustrates the scenario where a nonresetable ip- op is fed by a resetable ip- op:
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module resetckt ( output reg oDat, input iReset, iClk, input iDat); reg datareg; always @(posedge iClk) if(!iReset) datareg <= 0; else begin datareg <= iDat; oDat <= datareg; end endmodule
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The second ip- op (oDat) will be synthesized with a ip- op that has a load or clock enable input driven by the reset of the rst. This is illustrated in Figure 10.8. This requires larger sequential elements as well as extra routing resources. If the two ip- ops are split according to the following code:
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module resetckt( output reg oDat, input iReset, iClk); input iDat); reg datareg; always @(posedge iClk) if(!iReset) datareg <= 0;
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10 Reset Circuits
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Figure 10.8 Implementation with mixed reset types.
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Figure 10.9 Optimal implementation with mixed reset types.
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else datareg <= iDat; always @(posedge iClk) oDat <= datareg; endmodule
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the second ip- op will have no unnecessary circuitry as represented in Figure 10.9. Different reset types should not be used in a single always block.
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Internally Generated Resets
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In some designs, there are conditions where an internal event will cause a reset condition for a portion of the chip. There are two options in this case:
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Using asynchronous resets, design the logic that derives the reset to be free of any static hazards. Use synchronous resets.
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The main problem with a static hazard on an asynchronous reset is that due to variances in propagation delays, a reset pulse could occur even though the logic is switching from one inactive state to another. Assuming an active low
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10.2 Mixing Reset Types
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Potential hazard on reset
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reset, a glitch on an inactive state would be de ned as a static-1 hazard. As an example, consider Figure 10.10. With the circuit in Figure 10.10, a static-1 hazard can occur during the transition (a, b, c) = (1, 0, 1) 2. (0, 0,1) as shown in Figure 10.11. As can be seen from the waveforms in Figure 10.11, a static-1 glitch can occur on the reset line when one of the terms that sets the output inactive (logic-1) becomes invalid before the next term sets the reset high. Remembering back to logic design 101, this can be represented in a K-map format as shown in Figure 10.12. Each circled region in Figure 10.12 indicates a product term that sets the reset inactive. The static-1 hazard occurs when the state of the inputs changes from one adjacent product term to another. If the rst product term becomes inactive before the second is set, a glitch will occur. To x this problem, a redundant prime implicant is created to bridge the two product terms as shown in Figure 10.13. By adding the new product term as indicated by the redundant logic mapping, we eliminate the possibility of a hazard that will cause a glitch while the reset is in the inactive state. In general, the technique for eliminating static-1 hazards will prevent a glitch on an internally generated reset line. However, the use of a fully synchronous
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Figure 10.11 Example waveform with reset hazard.
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10 Reset Circuits
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Identifying the static-1 hazard.
Adding a prime implicant.
reset synchronizer is typically recommended in practice. This helps to maintain a fully synchronous design and to eliminate the redundant logic necessary to maintain a glitch-free reset signal.
10.3 MULTIPLE CLOCK DOMAINS
We have already established that reset deassertion must always be synchronous and that asynchronous reset signals must be resynchronized for deassertion. As an
Reset synchronization with multiple clock domains.
10.4 Summary of Key Points
extension of this principle, it is important to synchronize resets independently for each asynchronous clock domain. As can be seen in Figure 10.14, a separate reset synchronization circuit is used for each clock domain. This is necessary because of the fact that a synchronous reset deassertion on one clock domain will not solve the clock recovery problems on an asynchronous clock domain. In other words, a synchronized reset signal will still be asynchronous relative to the synchronized reset from an independent clock domain.