Figure 6.10 Resynchronization of analog feedback. in .NET framework

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Figure 6.10 Resynchronization of analog feedback.
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6 Clock Domains Timing analysis should ignore the rst resynchronization ip- op and ensure that the timing between the synchronization ip- ops themselves is minimized.
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Solution 3: FIFO Structure
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A more sophisticated way of passing data between clock domains is through the use of a rst-in, rst-out (FIFO) structure. FIFOs can be used when passing multibit signals between asynchronous clock domains. Very common applications for FIFOs include passing data between standardized bus interfaces and reading/ writing burstable memory. For example, Figure 6.11 illustrates the interface between burstable memory and a PCI bus.
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Figure 6.11 FIFO in a PCI Application.
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6.1 Crossing Clock Domains FIFOs can be used when passing multibit signals between asynchronous clock domains.
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FIFOs are very useful data structures for a variety of applications, but in the context of this discussion we will be concerned with its ability to handle bursts of data that need to be passed between clock domains. The simplest analogy for a FIFO is a line at the supermarket. Customers arrive at the checkout at more or less random times and at a particular average frequency. Sometimes there will be little traf c, and at other times there will be bursts of customers. The cashiers at the checkout cannot immediately service every customer as they arrive, and thus a line forms. In an abstract sense, a line of data is called a queue. Subsequently, the cashiers proceed to service the customers at a more or less constant frequency regardless of the length of the line. If the average rate of customers exceeds the rate at which they can be serviced, the structure will be unsustainable. At that point, either another mechanism must be put in place to service the customers at a faster rate or the rate of new customers must decrease. The same principles hold for many types of data transfers. Data may arrive on one clock domain at essentially random time intervals, some of which may contain large bursts of traf c. The receiving device, in this case sitting on a different clock domain, can only process the data at a particular rate. The queue that is formed takes place inside a device called a FIFO as shown in Figure 6.12. With an asynchronous FIFO, data can arrive at arbitrary time intervals on the transmission side, and the receiving side pulls data out of the queue as it has the bandwidth to process it. Due to the nite size of any queue implemented with a FIFO, certain controls need to be in place to prevent an over ow. Two options are available for this scenario:
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Prior knowledge of the transmission rate (burstable or nonburstable), the minimum receiving rate, and the corresponding maximum queue size. Handshaking controls.
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Note that it is not necessary for the clock domain of the transmission device to run at a faster frequency than the clock domain of the receiving device for an over ow to occur. A slower clock domain may require fewer clock cycles to pass
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Figure 6.12 Asynchronous FIFO.
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6 Clock Domains
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data to the FIFO than the number of clock cycles for the receiving side to process the data. Thus, if handshaking controls are not in place, it is critically important to understand the worst-case scenario as described above. Note that if the transmitting side passes data to the FIFO at a rate faster than the receiving side can handle it for an arbitrary amount of time, the system simply will become unsustainable as the queue increases inde nitely. Because no memory device can store an unlimited amount of data, this issue would need to be addressed at the system architecture level. In general, the transmissions will arrive in bursts separated by periods of little or no activity. The maximum FIFO size would then need to be equal to or greater than (depending on the properties of the receiver) the size of the burst. In many cases, neither the size of the bursts nor the distribution of the arriving data can be well de ned. In this case, handshaking controls are necessary to control the data ow into the FIFO. This is often implemented with ags as shown in Figure 6.13. These include a full ag to inform the transmitting side that there is no more room in the FIFO and an empty ag to inform the receiving side that there is no more data to fetch. A state machine may be needed to manage the handshaking controls as illustrated in Figure 6.13. FIFOs in FPGAs are typically implemented with a wrapper around a dualport RAM. The seemingly trivial ags such as full and empty are in reality the dif cult features to implement. The reason is because the ags for the input controls are often generated by the output stage, and similarly the ags for the output controls are often generated by the input stage. For instance, the logic that drives the input data must know whether or not the FIFO is full. This can only be determined by the amount of data that has been read by the output stage. Likewise, the logic that reads the data at the output stage must know if there is any new data available (whether the FIFO is empty). This can only be determined based on the write pointer from the input stage. The purpose of the FIFO in this context is to handle the data transfer between asynchronous clock domains, but in the implementation of the FIFO itself we run into the same problems with respect to the handshaking ags. To pass the necessary signals from one domain to the other, we must revert to a technique such as double opping as discussed in the previous section. Consider the diagram of a simpli ed asynchronous FIFO as shown in Figure 6.14. In Figure 6.14, both the write address and read address must be resynchronized when passed to the other domain for empty and full generation. The problem that arises is that during the resynchronization of a multibit address, some of the bits may lag others by a clock cycle, depending on the individual propagation times of the individual traces. In other words, due to the asynchronous nature of the two clock domains, some bits may be captured on one edge of the capture clock, and the others may be captured on the next depending on whether the data arrives at the rst ip- op with suf cient time prior to the clock edge. This could be disastrous if some of the bits of a binary address change and others do not, as the receiving logic will see a completely invalid address not equal to either the previous or current address.
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