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4 Example Design: The Advanced Encryption Standard
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inverse for an arbitrary polynomial bx c is given by: (bx c) 1 b(b2B bcA c2) 1 x (c bA)(b2B bcA c2) 1 The problem of calculating the inverse in GF(256) is now translated to calculating the inverse in GF(16) and performing some arithmetic operations in GF(16). The inverse in GF(16) can be stored in a much smaller table relative to the mapping in GF(256) and will correspond with an even more compact S-box implementation.
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High-Level Design
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Due to the increasing complexity of FPGA designs as well as the increasing
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sophistication and capability of the corresponding design tools, there will always be an increasing in demand for the ability to model a design with higher levels of abstraction. The move from schematic-based design to HDL (Hardware Description Language) design was revolutionary. It allowed a designer to describe modules in a behavioral fashion that was theoretically technology independent. There are many aspects of digital design with HDL that have become monotonous and time consuming and where higher levels of abstraction are obvious ts and have natural paths of progression. Other technologies that have been introduced over the past decade have had a dif cult time migrating to mainstream because (and this point can be argued) the t has been less obvious. This chapter discusses a number of high-level design techniques that have been found to provide utility to FPGA design engineers. During the course of this chapter, we will discuss the following topics in detail:
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Abstract state-machine design using graphical tools DSP design using MATLAB and Synplify DSP Software/hardware codesign
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ABSTRACT DESIGN TECHNIQUES
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In the 17th century, the mathematician Leibniz postulated that a mathematical theory must be simpler than the system it describes, otherwise it has no use as a theory. This is a very profound statement and one that has a direct corollary to modern engineering. If a new form of abstract design is not simpler to comprehend or easier to design with than a previous form, then it is of little or no use to us in the real world. Some high-level design techniques that have been developed
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Advanced FPGA Design. By Steve Kilts Copyright # 2007 John Wiley & Sons, Inc.
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5 High-Level Design
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over the past 10 15 years certainly fall under the category of lateral abstraction, or new design techniques that are no more abstract than existing technologies. These technologies are slow to catch on; that is, if there is any bene t at all. This chapter discusses techniques that do provide the true bene ts of abstraction and that can increase the effectiveness of a designer.
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GRAPHICAL STATE MACHINES
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One obvious t for high-level design techniques is that of state-machine creation. Remembering back to our rst course in logic design, we learned to design state machines by rst drawing a state-transition diagram and then translating this to HDL (or gates as the course may be) manually. The state-diagram representation is a natural abstraction that ts well with our existing design process. One feature of describing state machines in HDL is the vast number of valid state-machine encodings that are available to the designer. There are statemachine encodings that are optimal for compact designs and those that are well suited for high-speed designs. Many of the variations have to do with designer preference, but this also introduces the possibility of human error, not to mention software translation error when recognizing a state-machine description. Oftentimes a designer does not have the knowledge whether one state-machine encoding will be optimal for his or her implementation until after synthesis has been performed. Modifying the state-machine encoding is time consuming and is generally not related to the functionality of the state machine. It is true that most synthesis tools will recognize a state machine and recode it based on the physical design constraints, but a higher-level description that gives the synthesis tool the most exibility regarding the implementation details is, in general, an optimal approach. Take for example the following state machine that loads a multiplier and accumulator for a low-pass DSP function:
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module shelflow( output reg output reg [23:0] output reg [23:0] output reg output reg [23:0] input input [23:0] input input [23:0] input input [23:0] multstart, multdat, multcoeff, clearaccum, U0, CLK, RESET, iData, // X[0] iWriteStrobe, // X[0] is valid iALow, iCLow, // coeffs for low pass filter multdone, accum);
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// define input/output samples reg [23:0] X0, X1, U1;
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5.2 Graphical State Machines // the registers that are multiplied together in mult24 reg [2:0] state; // holds state for sequencing through mults parameter State0 State1 State2 State3 = = = = 0, 1, 2, 3;
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always @(posedge CLK) if(!RESET) begin X0 <= 0; X1 <= 0; U0 <= 0; U1 <= 0; multstart <= 0; multdat <= 0; multcoeff <= 0; state <= State0; clearaccum <= 0; end else begin // do not process state machine if multiply is not done case(state) State0: begin // idle state if(iWriteStrobe) begin // if a new sample has arrived // shift samples X0 <= iData; X1 <= X0; U1 <= U0; multdat <= iData; // load mult multcoeff <= iALow; multstart <= 1; clearaccum <= 1; // clear accum state <= State1; end else begin multstart <= 0; clearaccum <= 0; end end State1: begin // A*X[0] is done, load A*X[1] if(multdone) begin multdat <= X1; multcoeff <= iALow;
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5 High-Level Design multstart state end else begin multstart clearaccum end end State2: begin // A*X[1] is if(multdone) multdat multcoeff multstart state end else begin multstart clearaccum end end State3: begin // C*U[1] is // [RL-1] U0 if(multdone) U0 state end else begin multstart clearaccum end end default state endcase end endmodule <= 1; <= State2;
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<= 0; <= 0;
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done, load C*U[1] begin <= U1; <= iCLow; <= 1; <= State3;
<= 0; <= 0;
done, load G*accum <= accumsum; begin <= accum; <= State0;
<= 0; <= 0;
<= State0;
The above module sequences through the operations for executing multiply and accumulate operations. For the purposes of this example, the multiplier and accumulator are located outside of this module. Let us take a look at the effect of describing this state machine in a more abstract format. There are a number of tools that can be used for graphical state-machine entry. To begin with, let us use the free Xilinx state-machine editor called StateCAD. The graphical state machine is represented in Figure 5.1.