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endmodule
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In this section, we discuss speed/area trade-offs for pipelined versus compact architectures and provide actual measurements from typical target technologies. All three architectures were designed with the same hardware description language (Verilog), and all used the same coding conventions. The rst target technology was a Xilinx Virtex II FPGA. The statistics are shown in Table 4.1. For comparison against the FPGA implementation, the design was also targeted to an 0.35 mm ASIC process as shown in Table 4.2. The performance metrics shown in the tables are de ned as follows: 1. LUTs: This represents the logic utilization that the AES core consumes inside the FPGA.
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Table 4.1 Speed/Area Statistics Targeting a Xilinx Virtex II Architecture Iterative Partially Pipelined Fully Pipelined Area (Xilinx LUTs) 886 4432 5894 Best Possible Throughput (MBPS) 340 15,400 15,400 Worst-Case Throughput 340 314 15,400
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Table 4.2 Speed/Area Statistics for an 0.35-mm AMI ASIC Architecture Iterative Partially Pipelined Fully Pipelined Area (ASIC Gates) 3321 15,191 25,758 Best Possible Throughput (MBPS) 788 40,064 40,064 Worst-Case Throughput 788 817 40,064
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Worst-case throughput assumes that a new key is introduced for every data block.
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4.3 Other Optimizations
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2. ASIC gates: This is the number of logic gates that is consumed by the AES core in an ASIC. 3. Best possible throughput: This is the maximum number of data bits that can be processed per second in the best-case scenario. Best case refers to the situation where there is the least amount of penalty delay due to expanding new keys. 4. Worst-case throughput: Worst case here refers to the situation where there is the greatest amount of penalty delay due to expanding new keys. This situation arises when every data block has a unique key. As can be seen from the data in Tables 4.1 and 4.2, the fully pipelined architecture is two orders of magnitude faster (in terms of throughput) under the worstcase scenario of a new key introduced for every data block. Note that the pipelined architecture is penalized for frequent key changes if it cannot ll the pipeline until previous encryptions are complete. This is what accounts for the drastic drop from best-case to worst-case throughput in the standard pipelined architecture.
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OTHER OPTIMIZATIONS
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As can be seen from the comparisons section, one of the primary issues with a fully pipelined design is area utilization. Also an issue with this pipelined architecture is the number of block RAMs needed to hold the S-box transformation look-up table. Many modern implementations use the block RAM LUT approach as it is easy to implement and can generate the necessary transformation in a single clock cycle. An arbitrary mapping over GF(28) will require one 8 256 RAM module. A single mapping would not cause an issue, but considering that approximately 320 look-ups need to be performed on every clock, this presents a major issue for FPGA implementations because this memory requirement pushes the limits of even the larger modern FPGAs. Another solution would be to implement the multiplicative inverse using the Extended Euclidean Algorithm as outlined in various technical references. However, the algorithm to compute the inverse of an arbitrary polynomial in GF(2m) has complexity of O(m) and requires 2 m calculations. These steps cannot be placed in parallel for ef cient hardware because each calculation depends on the previous. This type of iterative algorithm may be acceptable for software implementations, but the latency in a hardware implementation (2 m Rounds 160 to 224 clocks) may be unacceptable for applications frequently encrypting small amounts of data. A third approach to implementing the S-box in hardware was proposed by Vincent Rijmen (one of the inventors of Rijndael). The idea is to represent every element of GF(256) as a polynomial of the rst degree with coef cients from GF(16). Denoting the irreducible polynomial as x2 Ax B, the multiplicative
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