Figure 4.8 Iterative key expansion. in Visual Studio .NET

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Figure 4.8 Iterative key expansion.
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Partially Pipelined Architecture
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The second implementation under consideration is a partially pipelined architecture. An AES round is completed in 11 to 14 clock cycles depending on the key size. As can be seen from Figure 4.9, multiple instantiations of the data path core can be used to create a pipelined design, where the key expansion is performed in a static fashion. This implementation is shown in the following code for Nk 4.
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module AES_core( output [32* Nb-1:0] oCiphertext, // output cipthertext output oValid, // data at output is valid // signals that new key has been completely processed output oKeysValid, input iClk, iReset, input [32* Nb-1:0] iPlaintext, // input data to be encrypted input [32* Nk-1:0] iKey, // input cipther key input iReady, // valid data to encrypt input iNewKey); // signals new key is input wire [32* Nb-1:0] wRoundKey1, wRoundKey2, wRoundKey3, wRoundKey4, wRoundKey5, wRoundKey6, wRoundKey7, wRoundKey8, wRoundKey9, wRoundKeyFinal, wRoundKeyInit; wire [32* Nb-1:0] wBlockOut1, wBlockOut2, wBlockOut3, wBlockOut4, wBlockOut5, wBlockOut6,
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Figure 4.9 A partially pipelined implementation.
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4 Example Design: The Advanced Encryption Standard wBlockOut7, wBlockOut8, wBlockOut9, wBlockOutInit; [32* Nk-1:0] wNkKeysInit; [3:0] wKeyIterInit; [3:0] wKeyIterModNkInit; [3:0] wKeyIterDivNkInit; wValid1, wValid2, wValid3, wValid4, wValid5, wValid6, wValid7, wValid8, wValid9, wValidFinal, wValidInit; wNewKeyInit; [128*( Nr+1)-1:0] wKeys; // complete set of round keys wKeyReg; wNewKeyReg, wReadyReg; wPlaintextReg; .iClk(iClk), .iReset(iReset), .iKey(iKey), .iNewKey(iNewKey), .iPlaintext(iPlaintext), .iReady(iReady), .oKey(wKeyReg), .oNewKey(wNewKeyReg), .oPlaintext(wPlaintextReg), .oReady(wReadyReg));
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wire wire wire wire wire
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// registered inputs wire [32* Nk-1:0] wire wire [127:0] // register inputs InputRegs InputRegs(
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// initial key expansion KeyExpInit KeyExpInit( .iClk(iClk), .iReset(iReset), .iNkKeys(wKeyReg), .iNewKey (wNewKeyReg), .oKeyIter(wKeyIterInit), .oNewKey(wNewKeyInit), .oKeyIterModNk (wKeyIterModNkInit), .oNkKeys(wNkKeysInit), .oKeyIterDivNk (wKeyIterDivNkInit)); // initial addition of round key AddRoundKey InitialKey( .iClk(iClk), .iReset(iReset), .iBlockIn(wPlaintextReg), .iRoundKey(wRoundKeyInit), .oBlockOut(wBlockOutInit), .iReady(wReadyReg), .oValid(wValidInit));
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// Number of rounds is a function of key size (10, 12, or 14) // Key expansion block KeyExpansion KeyExpansion( .iClk(iClk), .iReset(iReset), .iKeyIter(wKeyIterInit), .iKeyIterModNk(wKeyIterMod NkInit), .iNkKeys(wNkKeysInit), .iKeyIterDivNk(wKeyIterDiv NkInit), .iNewKey(wNewKeyInit), .oKeys(wKeys), .oKeysValid (oKeysValid));
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// round transformation blocks Round R1( .iClk(iClk), .iReset (iReset), .iBlockIn(wBlockOutInit), .iRoundKey(wRoundKey1), .oBlockOut(wBlockOut1), .iReady(wValidInit), .oValid(wValid1)); Round R9( .iClk(iClk), .iReset (iReset), .iBlockIn(wBlockOut8), .iRoundKey(wRoundKey9), .oBlockOut(wBlockOut9), .iReady(wValid8), .oValid(wValid9));
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// 10 rounds total // Initial key addition assign wRoundKeyFinal = wKeys[128*( Nr-7)-1: 128*( Nr-8)]; // round key assignments assign wRoundKey9 = wKeys[128*( Nr-6)-1: 128*( Nr-7)]; assign wRoundKey8 = wKeys[128*( Nr-5)-1: 128*( Nr-6)]; assign wRoundKey7 = wKeys[128*( Nr-4)-1: 128*( Nr-5)]; assign wRoundKey6 = wKeys[128*( Nr-3)-1: 128*( Nr-4)]; assign wRoundKey5 = wKeys[128*( Nr-2)-1: 128*( Nr-3)]; assign wRoundKey4 = wKeys[128*( Nr-1)-1: 128*( Nr-2)]; assign wRoundKey3 = wKeys[128* Nr-1: 128*( Nr-1)]; assign wRoundKey2 = wKeys[128*( Nr+1)-1: 128* Nr]; assign wRoundKey1 = wNkKeysInit[128-1:0]; assign wRoundKeyInit = iKey[128-1:0];
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4 Example Design: The Advanced Encryption Standard FinalRound FinalRound( .iClk(iClk), .iReset(iReset), .iBlockIn(wBlockOut9), .iRoundKey(wRoundKeyFinal), .oBlockOut(oCiphertext), .iReady(wValid9), .oValid (oValid));
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endmodule
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Although pipelined designs such as the one above can potentially encrypt data at fast data rates, a problem arises in these architectures if one were to introduce new keys at a rate faster than the encryption speed. The surrounding system would have to be smart enough to wait for the pipe to empty before introducing the new data block along with the new key. This information has to be fed back to the outside system that is providing the information and the corresponding keys so that they can be buffered and held appropriately. In the worst case where a new key is required for every block of data, the pipelined architecture would have a throughput equivalent to that of the iterative architecture and would be a massive waste of space (not to mention the disappointment of not achieving the advertised throughput). The next section presents an architecture that eliminates this problem.
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Fully Pipelined Architecture
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The term fully pipelined refers to an architecture for the key expansion that runs in parallel to the round transformation pipeline, where corresponding stages in the pipeline provide each other with the exact information at just the right time. In other words, the round key for any particular stage and any particular data block is valid for only one clock cycle and is used by the corresponding round at that time. This occurs in parallel for every pipeline stage. Thus, a unique key may be used for potentially every block of data, with no penalization in terms of latency or wait states. The maximum throughput of the round transformation pipeline is always achieved independent of the topology of the key set. A block diagram for the fully pipelined implementation is shown in Figure 4.10. This means that a single iteration through the Key Expansion function (four 32-bit word expansion of the key) would happen fully synchronous with the round previous to the round that the key being generated would be used. Also, the latency for the Key Expansion block would have to maintain a clock latency equal to that of the Round block, typically equal to 1 4 clocks. For the round key at any arbitrary key expansion block to arrive at its corresponding Round block appropriately, and on potentially every clock pulse, the timing must be very precise. Speci cally, each key expansion block must generate a round key in exactly the same number of clock cycles that the Round block can generate its corresponding data. Also, the latency must be such that each key is valid when presented to the add-round-key sub-block. To handle these requirements, each key expansion block is divided into four incremental expansion
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