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0; 0; 0; 0; 0;
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4 Example Design: The Advanced Encryption Standard oKeyIter OldKeys <= iKeyIter + 1; <= iNkKeys;
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// update "Key iteration mod Nk" for next iteration if(iKeyIterModNk + 1 == Nk) begin oKeyIterModNk <= 0; oKeyIterDivNk <= iKeyIterDivNk+1; end else begin oKeyIterModNk <= iKeyIterModNk + 1; oKeyIterDivNk <= iKeyIterDivNk; end if(iKeyIterModNk == 0) InterKey <= SubWord ^ Rcon; ifdef Nk8 // an option only for Nk = 8 else if(iKeyIterModNk == 4) InterKey <= SubWordNk8; endif else InterKey <= PrevKey; end endmodule
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Likewise, the autonomous operation for the data path is the combination of all functions required for a round encryption as shown in the following implementation.
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module RoundEnc( output [32* Nb-1:0] output input input [32* Nb-1:0] input input [3:0] wire [32* Nb-1:0] wire SubBytesEnc sub( oBlockOut, oValid, iClk, iReset, iBlockIn, iRoundKey, iReady, iRound); wSubOut, wShiftOut, wMixOut; wValidSub, wValidShift, wValidMix; .iClk(iClk), .iReset(iReset), .iBlockIn(iBlockIn), .oBlockOut(wSubOut), .iReady(iReady), .oValid(wValidSub)); .iBlockIn(wSubOut), .oBlock Out(wShiftOut), .iReady(wValidSub), .oValid (wValidShift)); .iClk(iClk), .iReset(iReset), .iBlockIn(wShiftOut),
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ShiftRowsEnc shift(
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MixColumnsEnc mixcolumn(
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4.1 AES Architectures .oBlockOut(wMixOut), .iReady(wValidShift), .oValid(wValidMix), .iRound(iRound));
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AddRoundKeyEnc addroundkey(.iClk(iClk), .iReset(iReset), .iBlockIn(wMixOut), .iRoundKey(iRoundKey), .oBlockOut(oBlockOut), .iReady(wValidMix), .oValid(oValid)); endmodule
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The implementation of the Round subblocks is straightforward. For reasons described later, assume that each Round has a latency of 4 clocks. It would be reasonable (based on logic balancing) to distribute the pipeline stages as follows.
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One Stage for Sub-bytes
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Sub-bytes is implemented as a look-up table due to the iterative nature of the algorithms implemented by it as well as the relatively small map space. Thus, an 8-bit to 8-bit mapping would be ef ciently implemented as a synchronous 8 256 (28) ROM with a single pipeline stage. This is shown in Figure 4.1.
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This stage simply mixes the rows in the data block, so no logic is used here. Thus, another pipeline stage at this point would create an imbalance of logic
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Figure 4.1 An 8-bit mapping in the sub-bytes module.
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4 Example Design: The Advanced Encryption Standard
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Figure 4.2 Shift-row implementation.
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around the pipeline stages and thus decrease maximum frequency and total throughput. The shifted rows are illustrated in Figure 4.2.
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This stage has the most logic out of all four Round stages and is thus the best place to add the additional pipeline stage. The mix-column hierarchy is shown in Figure 4.3. As can be seen from Figure 4.3, Mix-Column uses a module called MapColumn as a building block. This can be seen in Figure 4.4. As can be seen from Figure 4.4, Map-Column uses a block called Poly-Mult X2 (polynomial 2 multiplier) as a building block. This is shown in Figure 4.5.
One Stage for Add Round Key
This stage simply XORs the round key from the key expansion pipeline with the data block. This is shown in Figure 4.6.
Figure 4.3 The mix-column hierarchy.
4.1 AES Architectures
Figure 4.4 The Map-column hierarchy.
Compact Architecture
The rst implementation under consideration is a compact implementation designed to iteratively reuse logic resources. Initially, the incoming data and key are added together in the Initial Round module, and the result is registered before entering the encryption loop. The data is then applied to the Sub Bytes, Shift Rows, Mult-Column, and Add Round Key in the speci ed order. At the end of each round, the new data is registered. These operations are repeated according to the number of rounds. A block diagram of the iterative architecture is shown in Figure 4.7. The top-level implementation is shown in the following code.
module AES_Enc_core( output [32* Nb-1:0] output output oCiphertext, // output cipthertext oValid, // data at output is valid oKeysValid,
Figure 4.5 Polynomial multiplication x2.
Figure 4.6 The add-round-key block.
4 Example Design: The Advanced Encryption Standard
Figure 4.7 A compact implementation.
input input [32* Nb-1:0] encrypted input [32* Nk-1:0] input input input // registered inputs wire [32* Nk-1:0] wire wire [127:0] wire [127:0]
iClk, iReset, iPlaintext, // input data to be iKey, // input cipther key iReady, // valid data to encrypt iNewKey); // signals new key is
wKeyReg; wNewKeyReg, wReadyReg; wPlaintextReg, wBlockOutInit; wRoundKeyInit, wRoundKey;
// register inputs InputRegsEnc InputRegs( .iClk(iClk), .iReset(iReset), .iKey(iKey), .iNewKey(iNewKey), .iPlaintext (iPlaintext), .oKeysValid(oKeysValid), .iReady(iReady), .oKey(wKeyReg), .oPlaintext (wPlaintextReg), .oReady(wReadyReg)); // initial addition of round key AddRoundKeyEnc InitialKey( .iClk(iClk), .iReset(iReset), .iBlockIn(wPlaintextReg), .iRoundKey(wRoundKeyInit), .oBlockOut(wBlockOutInit), .iReady(wReadyReg), .oValid(wValidInit)); // Number of rounds is a function of key size (10, 12, or 14) // Key expansion block
4.1 AES Architectures KeyExpansionEnc KeyExpansion( .iClk(iClk), .iReset (iReset), .iNkKeys(wKeyReg), .iReady(wReadyReg), .oRoundKey(wRoundKey)); RoundsIterEnc RoundsIter(
.iClk(iClk), .iReset(iReset), .iBlockIn(wBlockOutInit), .oBlockOut(oCiphertext), .iReady(wValidInit), .oValid(oValid), .iRoundKey(wRoundKey));
ifdef Nk4 assign wRoundKeyInit = wKeyReg[128-1:0]; endif ifdef Nk6 assign wRoundKeyInit = wKeyReg[192-1:192-128]; endif ifdef Nk8 assign wRoundKeyInit = wKeyReg[256-1:256-128]; endif endmodule
In the above code, the modules KeyExpansionEnc and RoundsIterEnc perform the iterative operations required of the compact architecture. The KeyExpansionEnc handles the iterations for the key expansion, and RoundsIterEnc handles the data path. A unique round key is passed from the key expansion module to RoundsIterEnc for every iteration of the round. The following code loops the key information through the same expansion module to reuse the logic for every round:
module KeyExpansionEnc( output [128-1:0] oRoundKey, input iClk, iReset, // The last Nk keys generated in initial key expansion input [32* Nk-1:0] iNkKeys, input iReady); // signals a new key is input wire [3:0] KeyIterIn, KeyIterOut; wire [3:0] KeyIterDivNkIn, KeyIterDivNkOut; wire [3:0] KeyIterModNkIn, KeyIterModNkOut; wire [32* Nk-1:0] NkKeysOut, NkKeysIn; wire wReady; assign wReady assign KeyIterIn assign oRoundKey = = = iReady; wReady Nk : KeyIterOut; NkKeysOut[32* Nk-1:32* Nk-128];
4 Example Design: The Advanced Encryption Standard assign KeyIterModNkIn = assign KeyIterDivNkIn = assign NkKeysIn = wReady 4 h0 : KeyIter ModNkOut; wReady 4 h1 : KeyIter DivNkOut; wReady iNkKeys : NkKeysOut;
KeyExp1Enc KeyExp1(.iClk(iClk), .iReset(iReset), .iKeyIter(KeyIterIn), .iKeyIterModNk(KeyIterModNkIn), .iNkKeys(NkKeysIn), .iKeyIterDivNk (KeyIterDivNkIn), .oKeyIter(KeyIterOut), .oKeyIterModNk(KeyIterModNkOut), .oNkKeys(NkKeysOut), .oKeyIterDivNk(KeyIterDivNkOut)); endmodule
In the above module, the output of the single key expansion module KeyExp1Enc is routed back to the input for further expansion on subsequent rounds as shown in Figure 4.8. Thus, the logic in the KeyExp1Enc is reused for every round.